Lluís Vilanova 9c489ea6be tcg: Pass generic CPUState to gen_intermediate_code() ... Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>		2017-07-19 14:45:16 -07:00
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core-dc232b
core-dc233c
core-fsf
core-dc232b.c
core-dc233c.c
core-fsf.c
cpu-qom.h
cpu.c	target-xtensa: implement RER/WER instructions	2017-01-16 19:19:03 -08:00
cpu.h	target/xtensa: support output to chardev console	2017-06-06 02:40:48 -07:00
gdbstub.c	target/xtensa: gdbstub: drop dead return statement	2017-07-11 11:18:37 +03:00
helper.c	target/xtensa: hold BQL for interrupt processing	2017-03-09 10:41:43 +00:00
helper.h	target/xtensa updates:	2017-01-25 16:36:57 +00:00
import_core.sh	target/xtensa: add two missing headers to core import script	2017-02-23 10:50:56 -08:00
Makefile.objs
monitor.c	monitor: Fix crashes when using HMP commands without CPU	2017-02-21 18:29:01 +00:00
op_helper.c	target/xtensa: hold BQL for interrupt processing	2017-03-09 10:41:43 +00:00
overlay_tool.h	target/xtensa: sim: instantiate local memories	2017-02-23 10:30:41 -08:00
translate.c	tcg: Pass generic CPUState to gen_intermediate_code()	2017-07-19 14:45:16 -07:00
xtensa-semi.c	char: add backend hotswap handler	2017-07-14 11:04:33 +02:00