qemu/target/ppc
Suraj Jitindar Singh d5fee0bbe6 target/ppc: Implement ISA V3.00 radix page fault handler
ISA V3.00 introduced a new radix mmu model. Implement the page fault
handler for this so we can run a tcg guest in radix mode and perform
address translation correctly.

In real mode (mmu turned off) addresses are masked to remove the top
4 bits and then are subject to partition scoped translation, since we only
support pseries at this stage it is only necessary to perform the masking
and then we're done.

In virtual mode (mmu turned on) address translation if performed as
follows:

1. Use the quadrant to determine the fully qualified address.

The fully qualified address is defined as the combination of the effective
address, the effective logical partition id (LPID) and the effective
process id (PID). Based on the quadrant (EA63:62) we set the pid and lpid
like so:

quadrant 0: lpid = LPIDR, pid = PIDR
quadrant 1: HV only (not allowed in pseries)
quadrant 2: HV only (not allowed in pseries)
quadrant 3: lpid = LPIDR, pid = 0

If we can't get the fully qualified address we raise a segment interrupt.

2. Find the guest radix tree

We ask the virtual hypervisor for the partition table which was registered
with H_REGISTER_PROC_TBL which points us to the process table in guest
memory. We then index this table by pid to get the process table entry
which points us to the appropriate radix tree to translate the address.

If the process table isn't big enough to contain an entry for the current
pid then we raise a storage interrupt.

3. Walk the radix tree

Next we walk the radix tree where each level is a table of page directory
entries indexed by some number of bits from the effective address, where
the number of bits is determined by the table size. We continue to walk
the tree (while entries are valid and the table is of minimum size) until
we reach a table of page table entries, indicated by having the leaf bit
set. The appropriate pte is then checked for sufficient access permissions,
the reference and change bits are updated and the real address is
calculated from the real page number bits of the pte and the low bits of
the effective address.

If we can't find an entry or can't access the entry bacause of permissions
then we raise a storage interrupt.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
[dwg: Add missing parentheses to macro]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-05-11 09:45:15 +10:00
..
translate target-ppc: Add xscvqpudz and xscvqpuwz instructions 2017-02-22 11:28:28 +11:00
arch_dump.c target/ppc: Fix size of struct PPCElfPrstatus 2017-04-26 12:41:55 +10:00
compat.c target/ppc: Add POWER9/ISAv3.00 to compat_table 2017-03-03 11:30:59 +11:00
cpu-models.c target/ppc/cpu-models: Fix/remove bad CPU aliases 2017-01-31 13:46:26 +11:00
cpu-models.h powerpc/cpu-models: rename ISAv3.00 logical PVR definition 2017-01-31 10:10:14 +11:00
cpu-qom.h spapr: Add ibm,processor-radix-AP-encodings to the device tree 2017-04-26 12:00:41 +10:00
cpu.c target/ppc: support for 32-bit carry and overflow 2017-03-01 11:23:39 +11:00
cpu.h target/ppc: Implement ISA V3.00 radix page fault handler 2017-05-11 09:45:15 +10:00
dfp_helper.c
excp_helper.c target/ppc: do not reset reserve_addr in exec_enter 2017-05-11 09:45:15 +10:00
fpu_helper.c target/ppc: use helper for excp handling 2017-03-06 13:17:28 +11:00
gdbstub.c
helper_regs.h cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
helper.h target/ppc: Flush TLB on write to PIDR 2017-04-26 12:41:56 +10:00
int_helper.c target/ppc: introduce helper_update_ov_legacy 2017-03-01 11:23:39 +11:00
internal.h target-ppc: implement load atomic instruction 2017-02-22 11:28:27 +11:00
kvm_ppc.h target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce 2017-04-26 12:00:41 +10:00
kvm-stub.c
kvm.c target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce 2017-04-26 12:00:41 +10:00
machine.c target/ppc: Manage external HPT via virtual hypervisor 2017-03-01 11:23:39 +11:00
Makefile.objs target/ppc: Implement ISA V3.00 radix page fault handler 2017-05-11 09:45:15 +10:00
mem_helper.c target-ppc: implement stxvll instructions 2017-01-31 10:10:13 +11:00
mfrom_table_gen.c
mfrom_table.c
misc_helper.c target/ppc: Flush TLB on write to PIDR 2017-04-26 12:41:56 +10:00
mmu_helper.c spapr: Small cleanup of PPC MMU enums 2017-03-03 11:30:59 +11:00
mmu-book3s-v3.c target/ppc: Implement ISA V3.00 radix page fault handler 2017-05-11 09:45:15 +10:00
mmu-book3s-v3.h target/ppc: Implement ISA V3.00 radix page fault handler 2017-05-11 09:45:15 +10:00
mmu-hash32.c target/ppc: Eliminate htab_base and htab_mask variables 2017-03-01 11:23:39 +11:00
mmu-hash32.h target/ppc: Manage external HPT via virtual hypervisor 2017-03-01 11:23:39 +11:00
mmu-hash64.c spapr: Small cleanup of PPC MMU enums 2017-03-03 11:30:59 +11:00
mmu-hash64.h target/ppc: Correct SDR1 masking 2017-03-01 11:23:39 +11:00
mmu-radix64.c target/ppc: Implement ISA V3.00 radix page fault handler 2017-05-11 09:45:15 +10:00
mmu-radix64.h target/ppc: Implement ISA V3.00 radix page fault handler 2017-05-11 09:45:15 +10:00
monitor.c monitor: Fix crashes when using HMP commands without CPU 2017-02-21 18:29:01 +00:00
STATUS
timebase_helper.c
trace-events
translate_init.c target/ppc: Change tlbie invalid fields for POWER9 support 2017-05-11 09:45:15 +10:00
translate.c target/ppc: Change tlbie invalid fields for POWER9 support 2017-05-11 09:45:15 +10:00
user_only_helper.c