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* hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled * hw/char/exynos4210_uart: Fix missing call to report ready for input * hw/arm/smmuv3: Fix addr_mask for range-based invalidation * hw/ssi/imx_spi: Fix various minor bugs * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register * hw/arm: Add missing Kconfig dependencies * hw/arm: Display CPU type in machine description -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmAaeAQZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3tWFD/9VTSSTmGMtSLGpuVt6t07x zqaFvRe+xUjrunwt25yx9tu9o4txXTk6mekgAz51QSeijESVIQQUKArZjbLWxRjl EXZAedOCF+f+lpzdQCO/GZtsHOfcWa158qm51NlEIM3cn1NiSASs0ky3r52MjjAR g0NFYTiZNplq8ah/0RljhHMhnAHzUbp/IErIxknWOVKvaH45+eji7mKxUk2vaCXB L5HCEzGCbPCqMMi3DFcwm9nNIYRu7X0hs9nR0AXTvdXbCoDqSyD4dEpjEcK/2IFM 4zbS4NFRD7ndjD0C502+EUFav3tfd5/UfIjNg3oquMTDQrMCvh5Y1i3II0lVVWe5 eSfbqV2eBzJHBanf7P64fRpk9mBNduJ8BZrozICvkCJxj5y3nTofKA9hXeGaDAdy 7sA7Uzkpb1vnnMFzYk/0t2D6BSSFiknYuDHnfMY0nRoHsuDvY5yHw9Tt181D+qST UyLcmS8BB227WGgQPKSsFiUu7U423BIoiD5pp8cRyAg+FojqH6BZrcVluUWng6Ru ZVG0349lTmZ4mgv2hZI1qqIh80o40TI6K7OerQuMkZlq+4xseZvyb6+SQHaQ/j3I CKBiN15y/UzE5eivG6Siq3MR2myCBCSevTxDw4s+zR9FhoRQqFKoDhPGXTR9btWo 1mgDNUQfyWtCcdoJKb7jEg== =kWoi -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210203' into staging target-arm queue: * hw/intc/arm_gic: Allow to use QTest without crashing * hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled * hw/char/exynos4210_uart: Fix missing call to report ready for input * hw/arm/smmuv3: Fix addr_mask for range-based invalidation * hw/ssi/imx_spi: Fix various minor bugs * hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register * hw/arm: Add missing Kconfig dependencies * hw/arm: Display CPU type in machine description # gpg: Signature made Wed 03 Feb 2021 10:16:36 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210203: (21 commits) hw/arm: Display CPU type in machine description hw/net/can: ZynqMP CAN device requires PTIMER hw/arm/xlnx-versal: Versal SoC requires ZynqMP peripherals hw/arm/xlnx-versal: Versal SoC requires ZDMA hw/arm/exynos4210: Add missing dependency on OR_IRQ hw/arm/stm32f405_soc: Add missing dependency on OR_IRQ hw/intc/arm_gic: Fix interrupt ID in GICD_SGIR register hw/ssi: imx_spi: Correct tx and rx fifo endianness hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Round up the burst length to be multiple of 8 hw/ssi: imx_spi: Disable chip selects when controller is disabled hw/ssi: imx_spi: Rework imx_spi_write() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_read() to handle block disabled hw/ssi: imx_spi: Rework imx_spi_reset() to keep CONREG register value hw/ssi: imx_spi: Remove pointless variable initialization hw/ssi: imx_spi: Remove imx_spi_update_irq() in imx_spi_reset() hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/arm/smmuv3: Fix addr_mask for range-based invalidation hw/char/exynos4210_uart: Fix missing call to report ready for input hw/char/exynos4210_uart: Fix buffer size reporting with FIFO disabled ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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