Markus Armbruster 75a6ed875f riscv: Fix to put "riscv.hart_array" devices on sysbus ... riscv_sifive_e_soc_init(), riscv_sifive_u_soc_init(), spike_board_init(), spike_v1_10_0_board_init(), spike_v1_09_1_board_init(), and riscv_virt_board_init() create "riscv-hart_array" sysbus devices in a way that leaves them unplugged. Create them the common way that puts them into the main system bus. Affects machines sifive_e, sifive_u, spike, spike_v1.10, spike_v1.9.1, and virt. Visible in "info qtree", here's the change for sifive_e: bus: main-system-bus type System + dev: riscv.hart_array, id "" + num-harts = 1 (0x1) + hartid-base = 0 (0x0) + cpu-type = "sifive-e31-riscv-cpu" dev: sifive_soc.gpio, id "" Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200609122339.937862-20-armbru@redhat.com>		2020-06-15 21:36:21 +02:00
..
boot.c	riscv: Change the default behavior if no -bios option is specified	2020-06-03 09:11:51 -07:00
Kconfig	riscv: Initial commit of OpenTitan machine	2020-06-03 09:11:51 -07:00
Makefile.objs	riscv: Initial commit of OpenTitan machine	2020-06-03 09:11:51 -07:00
opentitan.c	riscv: Fix to put "riscv.hart_array" devices on sysbus	2020-06-15 21:36:21 +02:00
riscv_hart.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
riscv_htif.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
sifive_clint.c	hw/riscv: Provide rdtime callback for TCG in CLINT emulation	2020-02-27 13:46:37 -08:00
sifive_e_prci.c	riscv: sifive_e: prci: Update the PRCI register block size	2019-09-17 08:42:46 -07:00
sifive_e.c	riscv: Fix to put "riscv.hart_array" devices on sysbus	2020-06-15 21:36:21 +02:00
sifive_gpio.c	Include migration/vmstate.h less	2019-08-16 13:31:52 +02:00
sifive_plic.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_test.c	riscv: hw: Remove the unnecessary include of target/riscv/cpu.h	2019-09-17 08:42:45 -07:00
sifive_u_otp.c	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
sifive_u_prci.c	riscv: sifive: Implement PRCI model for FU540	2019-09-17 08:42:47 -07:00
sifive_u.c	riscv: Fix to put "riscv.hart_array" devices on sysbus	2020-06-15 21:36:21 +02:00
sifive_uart.c	chardev: Use QEMUChrEvent enum in IOEventHandler typedef	2020-01-08 11:15:35 +01:00
spike.c	riscv: Fix to put "riscv.hart_array" devices on sysbus	2020-06-15 21:36:21 +02:00
trace-events	SiFive RISC-V GPIO Device	2019-05-24 11:58:30 -07:00
virt.c	riscv: Fix to put "riscv.hart_array" devices on sysbus	2020-06-15 21:36:21 +02:00