mirror of
https://github.com/qemu/qemu.git
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a99761d3c8
When an IOMMUMemoryRegion is in front of a virtio device,
address_space_cache_init does not set cache->ptr as the memory
region is not RAM. However when the device performs an access,
we end up in glue() which performs the translation and then uses
MAP_RAM. This latter uses the unset ptr and returns a wrong value
which leads to a SIGSEV in address_space_lduw_internal_cached_slow,
for instance.
In slow path cache->ptr is NULL and MAP_RAM must redirect to
qemu_map_ram_ptr((mr)->ram_block, ofs).
As MAP_RAM, IS_DIRECT and INVALIDATE are the same in _cached_slow
and non cached mode, let's remove those macros.
This fixes the use cases featuring vIOMMU (Intel and ARM SMMU)
which lead to a SIGSEV.
Fixes: 48564041a7 (exec: reintroduce MemoryRegion caching)
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-Id: <1528895946-28677-1-git-send-email-eric.auger@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
581 lines
16 KiB
C
581 lines
16 KiB
C
/*
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* Physical memory access templates
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2015 Linaro, Inc.
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* Copyright (c) 2016 Red Hat, Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* warning: addr must be aligned */
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static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (l < 4 || !memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 4, attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap32(val);
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}
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#endif
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = ldl_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = ldl_be_p(ptr);
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break;
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default:
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val = ldl_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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return val;
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}
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uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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/* warning: addr must be aligned */
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static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 8;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (l < 8 || !memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 8, attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap64(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap64(val);
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}
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#endif
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = ldq_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = ldq_be_p(ptr);
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break;
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default:
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val = ldq_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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return val;
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}
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uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (!memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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val = ldub_p(ptr);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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return val;
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}
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/* warning: addr must be aligned */
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static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 2;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (l < 2 || !memory_access_is_direct(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, 2, attrs);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap16(val);
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}
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#endif
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = lduw_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = lduw_be_p(ptr);
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break;
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default:
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val = lduw_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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return val;
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}
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uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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/* warning: addr must be aligned. The ram page is not masked as dirty
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and the code inside is not invalidated. It is useful if the dirty
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bits are used to track modified PTEs */
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void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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uint8_t dirty_log_mask;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
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} else {
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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stl_p(ptr, val);
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dirty_log_mask = memory_region_get_dirty_log_mask(mr);
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dirty_log_mask &= ~(1 << DIRTY_MEMORY_CODE);
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cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
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4, dirty_log_mask);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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}
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/* warning: addr must be aligned */
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static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs,
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MemTxResult *result, enum device_endian endian)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap32(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap32(val);
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}
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#endif
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r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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stl_le_p(ptr, val);
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break;
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case DEVICE_BIG_ENDIAN:
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stl_be_p(ptr, val);
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break;
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default:
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stl_p(ptr, val);
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break;
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}
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invalidate_and_set_dirty(mr, addr1, 4);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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}
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void glue(address_space_stl, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
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result, DEVICE_NATIVE_ENDIAN);
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}
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void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
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result, DEVICE_LITTLE_ENDIAN);
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}
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void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
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result, DEVICE_BIG_ENDIAN);
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}
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void glue(address_space_stb, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (!memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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stb_p(ptr, val);
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invalidate_and_set_dirty(mr, addr1, 1);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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}
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/* warning: addr must be aligned */
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static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs,
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MemTxResult *result, enum device_endian endian)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 2;
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hwaddr addr1;
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MemTxResult r;
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bool release_lock = false;
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 2 || !memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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#if defined(TARGET_WORDS_BIGENDIAN)
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if (endian == DEVICE_LITTLE_ENDIAN) {
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val = bswap16(val);
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}
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#else
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if (endian == DEVICE_BIG_ENDIAN) {
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val = bswap16(val);
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}
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#endif
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r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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stw_le_p(ptr, val);
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break;
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case DEVICE_BIG_ENDIAN:
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stw_be_p(ptr, val);
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break;
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default:
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stw_p(ptr, val);
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break;
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}
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invalidate_and_set_dirty(mr, addr1, 2);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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}
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void glue(address_space_stw, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_LITTLE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs,
|
|
MemTxResult *result, enum device_endian endian)
|
|
{
|
|
uint8_t *ptr;
|
|
MemoryRegion *mr;
|
|
hwaddr l = 8;
|
|
hwaddr addr1;
|
|
MemTxResult r;
|
|
bool release_lock = false;
|
|
|
|
RCU_READ_LOCK();
|
|
mr = TRANSLATE(addr, &addr1, &l, true, attrs);
|
|
if (l < 8 || !memory_access_is_direct(mr, true)) {
|
|
release_lock |= prepare_mmio_access(mr);
|
|
|
|
#if defined(TARGET_WORDS_BIGENDIAN)
|
|
if (endian == DEVICE_LITTLE_ENDIAN) {
|
|
val = bswap64(val);
|
|
}
|
|
#else
|
|
if (endian == DEVICE_BIG_ENDIAN) {
|
|
val = bswap64(val);
|
|
}
|
|
#endif
|
|
r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
|
|
} else {
|
|
/* RAM case */
|
|
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
|
|
switch (endian) {
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
stq_le_p(ptr, val);
|
|
break;
|
|
case DEVICE_BIG_ENDIAN:
|
|
stq_be_p(ptr, val);
|
|
break;
|
|
default:
|
|
stq_p(ptr, val);
|
|
break;
|
|
}
|
|
invalidate_and_set_dirty(mr, addr1, 8);
|
|
r = MEMTX_OK;
|
|
}
|
|
if (result) {
|
|
*result = r;
|
|
}
|
|
if (release_lock) {
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
RCU_READ_UNLOCK();
|
|
}
|
|
|
|
void glue(address_space_stq, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_LITTLE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
#undef ARG1_DECL
|
|
#undef ARG1
|
|
#undef SUFFIX
|
|
#undef TRANSLATE
|
|
#undef RCU_READ_LOCK
|
|
#undef RCU_READ_UNLOCK
|