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d2f9a79a8c
The nrf51_timer has a free-running counter which we implement using the pattern of using two fields (update_counter_ns, counter) to track the last point at which we calculated the counter value, and the counter value at that time. Then we can find the current counter value by converting the difference in wall-clock time between then and now to a tick count that we need to add to the counter value. Unfortunately the nrf51_timer's implementation of this has a bug which means it loses time every time update_counter() is called. After updating s->counter it always sets s->update_counter_ns to 'now', even though the actual point when s->counter hit the new value will be some point in the past (half a tick, say). In the worst case (guest code in a tight loop reading the counter, icount mode) the counter is continually queried less than a tick after it was last read, so s->counter never advances but s->update_counter_ns does, and the guest never makes forward progress. The fix for this is to only advance update_counter_ns to the timestamp of the last tick, not all the way to 'now'. (This is the pattern used in hw/misc/mps2-fpgaio.c's counter.) Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20230606134917.3782215-1-peter.maydell@linaro.org
410 lines
12 KiB
C
410 lines
12 KiB
C
/*
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* nRF51 System-on-Chip Timer peripheral
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*
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* Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
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* Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf
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*
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* Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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* Copyright (c) 2019 Red Hat, Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/arm/nrf51.h"
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#include "hw/irq.h"
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#include "hw/timer/nrf51_timer.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#define TIMER_CLK_FREQ 16000000UL
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static uint32_t const bitwidths[] = {16, 8, 24, 32};
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static uint32_t ns_to_ticks(NRF51TimerState *s, int64_t ns)
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{
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uint32_t freq = TIMER_CLK_FREQ >> s->prescaler;
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return muldiv64(ns, freq, NANOSECONDS_PER_SECOND);
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}
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static int64_t ticks_to_ns(NRF51TimerState *s, uint32_t ticks)
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{
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uint32_t freq = TIMER_CLK_FREQ >> s->prescaler;
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return muldiv64(ticks, NANOSECONDS_PER_SECOND, freq);
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}
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/* Returns number of ticks since last call */
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static uint32_t update_counter(NRF51TimerState *s, int64_t now)
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{
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uint32_t ticks = ns_to_ticks(s, now - s->update_counter_ns);
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s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]);
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/*
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* Only advance the sync time to the timestamp of the last tick,
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* not all the way to 'now', so we don't lose time if we do
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* multiple resyncs in a single tick.
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*/
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s->update_counter_ns += ticks_to_ns(s, ticks);
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return ticks;
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}
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/* Assumes s->counter is up-to-date */
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static void rearm_timer(NRF51TimerState *s, int64_t now)
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{
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int64_t min_ns = INT64_MAX;
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size_t i;
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for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) {
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int64_t delta_ns;
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if (s->events_compare[i]) {
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continue; /* already expired, ignore it for now */
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}
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if (s->cc[i] <= s->counter) {
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delta_ns = ticks_to_ns(s, BIT(bitwidths[s->bitmode]) -
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s->counter + s->cc[i]);
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} else {
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delta_ns = ticks_to_ns(s, s->cc[i] - s->counter);
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}
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if (delta_ns < min_ns) {
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min_ns = delta_ns;
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}
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}
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if (min_ns != INT64_MAX) {
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timer_mod_ns(&s->timer, now + min_ns);
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}
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}
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static void update_irq(NRF51TimerState *s)
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{
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bool flag = false;
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size_t i;
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for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) {
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flag |= s->events_compare[i] && extract32(s->inten, 16 + i, 1);
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}
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qemu_set_irq(s->irq, flag);
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}
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static void timer_expire(void *opaque)
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{
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NRF51TimerState *s = NRF51_TIMER(opaque);
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int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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uint32_t cc_remaining[NRF51_TIMER_REG_COUNT];
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bool should_stop = false;
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uint32_t ticks;
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size_t i;
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for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) {
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if (s->cc[i] > s->counter) {
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cc_remaining[i] = s->cc[i] - s->counter;
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} else {
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cc_remaining[i] = BIT(bitwidths[s->bitmode]) -
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s->counter + s->cc[i];
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}
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}
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ticks = update_counter(s, now);
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for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) {
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if (cc_remaining[i] <= ticks) {
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s->events_compare[i] = 1;
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if (s->shorts & BIT(i)) {
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s->timer_start_ns = now;
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s->update_counter_ns = s->timer_start_ns;
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s->counter = 0;
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}
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should_stop |= s->shorts & BIT(i + 8);
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}
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}
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update_irq(s);
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if (should_stop) {
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s->running = false;
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timer_del(&s->timer);
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} else {
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rearm_timer(s, now);
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}
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}
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static void counter_compare(NRF51TimerState *s)
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{
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uint32_t counter = s->counter;
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size_t i;
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for (i = 0; i < NRF51_TIMER_REG_COUNT; i++) {
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if (counter == s->cc[i]) {
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s->events_compare[i] = 1;
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if (s->shorts & BIT(i)) {
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s->counter = 0;
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}
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}
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}
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}
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static uint64_t nrf51_timer_read(void *opaque, hwaddr offset, unsigned int size)
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{
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NRF51TimerState *s = NRF51_TIMER(opaque);
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uint64_t r = 0;
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switch (offset) {
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case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
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r = s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4];
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break;
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case NRF51_TIMER_REG_SHORTS:
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r = s->shorts;
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break;
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case NRF51_TIMER_REG_INTENSET:
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r = s->inten;
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break;
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case NRF51_TIMER_REG_INTENCLR:
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r = s->inten;
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break;
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case NRF51_TIMER_REG_MODE:
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r = s->mode;
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break;
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case NRF51_TIMER_REG_BITMODE:
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r = s->bitmode;
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break;
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case NRF51_TIMER_REG_PRESCALER:
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r = s->prescaler;
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break;
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case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3:
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r = s->cc[(offset - NRF51_TIMER_REG_CC0) / 4];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: bad read offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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trace_nrf51_timer_read(s->id, offset, r, size);
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return r;
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}
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static void nrf51_timer_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned int size)
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{
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NRF51TimerState *s = NRF51_TIMER(opaque);
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uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
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size_t idx;
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trace_nrf51_timer_write(s->id, offset, value, size);
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switch (offset) {
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case NRF51_TIMER_TASK_START:
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if (value == NRF51_TRIGGER_TASK && s->mode == NRF51_TIMER_TIMER) {
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s->running = true;
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s->timer_start_ns = now - ticks_to_ns(s, s->counter);
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s->update_counter_ns = s->timer_start_ns;
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rearm_timer(s, now);
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}
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break;
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case NRF51_TIMER_TASK_STOP:
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case NRF51_TIMER_TASK_SHUTDOWN:
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if (value == NRF51_TRIGGER_TASK) {
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s->running = false;
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timer_del(&s->timer);
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}
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break;
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case NRF51_TIMER_TASK_COUNT:
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if (value == NRF51_TRIGGER_TASK && s->mode == NRF51_TIMER_COUNTER) {
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s->counter = (s->counter + 1) % BIT(bitwidths[s->bitmode]);
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counter_compare(s);
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}
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break;
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case NRF51_TIMER_TASK_CLEAR:
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if (value == NRF51_TRIGGER_TASK) {
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s->timer_start_ns = now;
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s->update_counter_ns = s->timer_start_ns;
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s->counter = 0;
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if (s->running) {
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rearm_timer(s, now);
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}
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}
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break;
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case NRF51_TIMER_TASK_CAPTURE_0 ... NRF51_TIMER_TASK_CAPTURE_3:
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if (value == NRF51_TRIGGER_TASK) {
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if (s->running) {
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timer_expire(s); /* update counter and all state */
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}
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idx = (offset - NRF51_TIMER_TASK_CAPTURE_0) / 4;
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s->cc[idx] = s->counter;
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trace_nrf51_timer_set_count(s->id, idx, s->counter);
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}
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break;
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case NRF51_TIMER_EVENT_COMPARE_0 ... NRF51_TIMER_EVENT_COMPARE_3:
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if (value == NRF51_EVENT_CLEAR) {
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s->events_compare[(offset - NRF51_TIMER_EVENT_COMPARE_0) / 4] = 0;
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if (s->running) {
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timer_expire(s); /* update counter and all state */
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}
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}
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break;
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case NRF51_TIMER_REG_SHORTS:
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s->shorts = value & NRF51_TIMER_REG_SHORTS_MASK;
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break;
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case NRF51_TIMER_REG_INTENSET:
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s->inten |= value & NRF51_TIMER_REG_INTEN_MASK;
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break;
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case NRF51_TIMER_REG_INTENCLR:
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s->inten &= ~(value & NRF51_TIMER_REG_INTEN_MASK);
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break;
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case NRF51_TIMER_REG_MODE:
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s->mode = value;
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break;
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case NRF51_TIMER_REG_BITMODE:
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if (s->mode == NRF51_TIMER_TIMER && s->running) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: erroneous change of BITMODE while timer is running\n",
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__func__);
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}
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s->bitmode = value & NRF51_TIMER_REG_BITMODE_MASK;
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break;
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case NRF51_TIMER_REG_PRESCALER:
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if (s->mode == NRF51_TIMER_TIMER && s->running) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: erroneous change of PRESCALER while timer is running\n",
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__func__);
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}
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s->prescaler = value & NRF51_TIMER_REG_PRESCALER_MASK;
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break;
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case NRF51_TIMER_REG_CC0 ... NRF51_TIMER_REG_CC3:
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if (s->running) {
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timer_expire(s); /* update counter */
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}
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idx = (offset - NRF51_TIMER_REG_CC0) / 4;
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s->cc[idx] = value % BIT(bitwidths[s->bitmode]);
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if (s->running) {
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rearm_timer(s, now);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: bad write offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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}
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update_irq(s);
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}
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static const MemoryRegionOps rng_ops = {
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.read = nrf51_timer_read,
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.write = nrf51_timer_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static void nrf51_timer_init(Object *obj)
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{
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NRF51TimerState *s = NRF51_TIMER(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->iomem, obj, &rng_ops, s,
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TYPE_NRF51_TIMER, NRF51_PERIPHERAL_SIZE);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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timer_init_ns(&s->timer, QEMU_CLOCK_VIRTUAL, timer_expire, s);
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}
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static void nrf51_timer_reset(DeviceState *dev)
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{
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NRF51TimerState *s = NRF51_TIMER(dev);
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timer_del(&s->timer);
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s->timer_start_ns = 0x00;
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s->update_counter_ns = 0x00;
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s->counter = 0x00;
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s->running = false;
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memset(s->events_compare, 0x00, sizeof(s->events_compare));
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memset(s->cc, 0x00, sizeof(s->cc));
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s->shorts = 0x00;
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s->inten = 0x00;
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s->mode = 0x00;
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s->bitmode = 0x00;
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s->prescaler = 0x00;
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}
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static int nrf51_timer_post_load(void *opaque, int version_id)
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{
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NRF51TimerState *s = NRF51_TIMER(opaque);
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if (s->running && s->mode == NRF51_TIMER_TIMER) {
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timer_expire(s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_nrf51_timer = {
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.name = TYPE_NRF51_TIMER,
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.version_id = 1,
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.post_load = nrf51_timer_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_TIMER(timer, NRF51TimerState),
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VMSTATE_INT64(timer_start_ns, NRF51TimerState),
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VMSTATE_INT64(update_counter_ns, NRF51TimerState),
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VMSTATE_UINT32(counter, NRF51TimerState),
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VMSTATE_BOOL(running, NRF51TimerState),
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VMSTATE_UINT8_ARRAY(events_compare, NRF51TimerState,
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NRF51_TIMER_REG_COUNT),
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VMSTATE_UINT32_ARRAY(cc, NRF51TimerState, NRF51_TIMER_REG_COUNT),
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VMSTATE_UINT32(shorts, NRF51TimerState),
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VMSTATE_UINT32(inten, NRF51TimerState),
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VMSTATE_UINT32(mode, NRF51TimerState),
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VMSTATE_UINT32(bitmode, NRF51TimerState),
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VMSTATE_UINT32(prescaler, NRF51TimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property nrf51_timer_properties[] = {
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DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void nrf51_timer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = nrf51_timer_reset;
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dc->vmsd = &vmstate_nrf51_timer;
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device_class_set_props(dc, nrf51_timer_properties);
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}
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static const TypeInfo nrf51_timer_info = {
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.name = TYPE_NRF51_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NRF51TimerState),
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.instance_init = nrf51_timer_init,
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.class_init = nrf51_timer_class_init
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};
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static void nrf51_timer_register_types(void)
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{
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type_register_static(&nrf51_timer_info);
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}
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type_init(nrf51_timer_register_types)
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