mirror of
https://github.com/qemu/qemu.git
synced 2024-11-26 04:13:39 +08:00
4c315c2766
Several devices don't survive object_unref(object_new(T)): they crash or hang during cleanup, or they leave dangling pointers behind. This breaks at least device-list-properties, because qmp_device_list_properties() needs to create a device to find its properties. Broken in commitf4eb32b
"qmp: show QOM properties in device-list-properties", v2.1. Example reproducer: $ qemu-system-aarch64 -nodefaults -display none -machine none -S -qmp stdio {"QMP": {"version": {"qemu": {"micro": 50, "minor": 4, "major": 2}, "package": ""}, "capabilities": []}} { "execute": "qmp_capabilities" } {"return": {}} { "execute": "device-list-properties", "arguments": { "typename": "pxa2xx-pcmcia" } } qemu-system-aarch64: /home/armbru/work/qemu/memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. Aborted (core dumped) [Exit 134 (SIGABRT)] Unfortunately, I can't fix the problems in these devices right now. Instead, add DeviceClass member cannot_destroy_with_object_finalize_yet to mark them: * Hang during cleanup (didn't debug, so I can't say why): "realview_pci", "versatile_pci". * Dangling pointer in cpus: most CPUs, plus "allwinner-a10", "digic", "fsl,imx25", "fsl,imx31", "xlnx,zynqmp", because they create such CPUs * Assert kvm_enabled(): "host-x86_64-cpu", host-i386-cpu", "host-powerpc64-cpu", "host-embedded-powerpc-cpu", "host-powerpc-cpu" (the powerpc ones can't currently reach the assertion, because the CPUs are only registered when KVM is enabled, but the assertion is arguably in the wrong place all the same) Make qmp_device_list_properties() fail cleanly when the device is so marked. This improves device-list-properties from "crashes, hangs or leaves dangling pointers behind" to "fails". Not a complete fix, just a better-than-nothing work-around. In the above reproducer, device-list-properties now fails with "Can't list properties of device 'pxa2xx-pcmcia'". This also protects -device FOO,help, which uses the same machinery since commitef52358
"qdev-monitor: include QOM properties in -device FOO, help output", v2.2. Example reproducer: $ qemu-system-aarch64 -machine none -device pxa2xx-pcmcia,help Before: qemu-system-aarch64: .../memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. After: Can't list properties of device 'pxa2xx-pcmcia' Cc: "Andreas Färber" <afaerber@suse.de> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Anthony Green <green@moxielogic.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Jia Liu <proljc@gmail.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Cc: qemu-ppc@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1443689999-12182-10-git-send-email-armbru@redhat.com>
200 lines
5.0 KiB
C
200 lines
5.0 KiB
C
/*
|
|
* QEMU UniCore32 CPU
|
|
*
|
|
* Copyright (c) 2010-2012 Guan Xuetao
|
|
* Copyright (c) 2012 SUSE LINUX Products GmbH
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* Contributions from 2012-04-01 on are considered under GPL version 2,
|
|
* or (at your option) any later version.
|
|
*/
|
|
|
|
#include "cpu.h"
|
|
#include "qemu-common.h"
|
|
#include "migration/vmstate.h"
|
|
|
|
static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
|
|
{
|
|
UniCore32CPU *cpu = UNICORE32_CPU(cs);
|
|
|
|
cpu->env.regs[31] = value;
|
|
}
|
|
|
|
static bool uc32_cpu_has_work(CPUState *cs)
|
|
{
|
|
return cs->interrupt_request &
|
|
(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
|
|
}
|
|
|
|
static inline void set_feature(CPUUniCore32State *env, int feature)
|
|
{
|
|
env->features |= feature;
|
|
}
|
|
|
|
/* CPU models */
|
|
|
|
static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model)
|
|
{
|
|
ObjectClass *oc;
|
|
char *typename;
|
|
|
|
if (cpu_model == NULL) {
|
|
return NULL;
|
|
}
|
|
|
|
typename = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, cpu_model);
|
|
oc = object_class_by_name(typename);
|
|
g_free(typename);
|
|
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) ||
|
|
object_class_is_abstract(oc))) {
|
|
oc = NULL;
|
|
}
|
|
return oc;
|
|
}
|
|
|
|
typedef struct UniCore32CPUInfo {
|
|
const char *name;
|
|
void (*instance_init)(Object *obj);
|
|
} UniCore32CPUInfo;
|
|
|
|
static void unicore_ii_cpu_initfn(Object *obj)
|
|
{
|
|
UniCore32CPU *cpu = UNICORE32_CPU(obj);
|
|
CPUUniCore32State *env = &cpu->env;
|
|
|
|
env->cp0.c0_cpuid = 0x4d000863;
|
|
env->cp0.c0_cachetype = 0x0d152152;
|
|
env->cp0.c1_sys = 0x2000;
|
|
env->cp0.c2_base = 0x0;
|
|
env->cp0.c3_faultstatus = 0x0;
|
|
env->cp0.c4_faultaddr = 0x0;
|
|
env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
|
|
|
|
set_feature(env, UC32_HWCAP_CMOV);
|
|
set_feature(env, UC32_HWCAP_UCF64);
|
|
}
|
|
|
|
static void uc32_any_cpu_initfn(Object *obj)
|
|
{
|
|
UniCore32CPU *cpu = UNICORE32_CPU(obj);
|
|
CPUUniCore32State *env = &cpu->env;
|
|
|
|
env->cp0.c0_cpuid = 0xffffffff;
|
|
env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
|
|
|
|
set_feature(env, UC32_HWCAP_CMOV);
|
|
set_feature(env, UC32_HWCAP_UCF64);
|
|
}
|
|
|
|
static const UniCore32CPUInfo uc32_cpus[] = {
|
|
{ .name = "UniCore-II", .instance_init = unicore_ii_cpu_initfn },
|
|
{ .name = "any", .instance_init = uc32_any_cpu_initfn },
|
|
};
|
|
|
|
static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
|
|
|
|
qemu_init_vcpu(CPU(dev));
|
|
|
|
ucc->parent_realize(dev, errp);
|
|
}
|
|
|
|
static void uc32_cpu_initfn(Object *obj)
|
|
{
|
|
CPUState *cs = CPU(obj);
|
|
UniCore32CPU *cpu = UNICORE32_CPU(obj);
|
|
CPUUniCore32State *env = &cpu->env;
|
|
static bool inited;
|
|
|
|
cs->env_ptr = env;
|
|
cpu_exec_init(cs, &error_abort);
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
env->uncached_asr = ASR_MODE_USER;
|
|
env->regs[31] = 0;
|
|
#else
|
|
env->uncached_asr = ASR_MODE_PRIV;
|
|
env->regs[31] = 0x03000000;
|
|
#endif
|
|
|
|
tlb_flush(cs, 1);
|
|
|
|
if (tcg_enabled() && !inited) {
|
|
inited = true;
|
|
uc32_translate_init();
|
|
}
|
|
}
|
|
|
|
static const VMStateDescription vmstate_uc32_cpu = {
|
|
.name = "cpu",
|
|
.unmigratable = 1,
|
|
};
|
|
|
|
static void uc32_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
|
|
|
|
ucc->parent_realize = dc->realize;
|
|
dc->realize = uc32_cpu_realizefn;
|
|
|
|
cc->class_by_name = uc32_cpu_class_by_name;
|
|
cc->has_work = uc32_cpu_has_work;
|
|
cc->do_interrupt = uc32_cpu_do_interrupt;
|
|
cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
|
|
cc->dump_state = uc32_cpu_dump_state;
|
|
cc->set_pc = uc32_cpu_set_pc;
|
|
#ifdef CONFIG_USER_ONLY
|
|
cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault;
|
|
#else
|
|
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
|
|
#endif
|
|
dc->vmsd = &vmstate_uc32_cpu;
|
|
|
|
/*
|
|
* Reason: uc32_cpu_initfn() calls cpu_exec_init(), which saves
|
|
* the object in cpus -> dangling pointer after final
|
|
* object_unref().
|
|
*/
|
|
dc->cannot_destroy_with_object_finalize_yet = true;
|
|
}
|
|
|
|
static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
|
|
{
|
|
TypeInfo type_info = {
|
|
.parent = TYPE_UNICORE32_CPU,
|
|
.instance_init = info->instance_init,
|
|
};
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, info->name);
|
|
type_register(&type_info);
|
|
g_free((void *)type_info.name);
|
|
}
|
|
|
|
static const TypeInfo uc32_cpu_type_info = {
|
|
.name = TYPE_UNICORE32_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(UniCore32CPU),
|
|
.instance_init = uc32_cpu_initfn,
|
|
.abstract = true,
|
|
.class_size = sizeof(UniCore32CPUClass),
|
|
.class_init = uc32_cpu_class_init,
|
|
};
|
|
|
|
static void uc32_cpu_register_types(void)
|
|
{
|
|
int i;
|
|
|
|
type_register_static(&uc32_cpu_type_info);
|
|
for (i = 0; i < ARRAY_SIZE(uc32_cpus); i++) {
|
|
uc32_register_cpu_type(&uc32_cpus[i]);
|
|
}
|
|
}
|
|
|
|
type_init(uc32_cpu_register_types)
|