mirror of
https://github.com/qemu/qemu.git
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44cbbf18b9
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2355 c046a42c-6fe2-441c-8c8c-71466251a162
222 lines
6.4 KiB
C
222 lines
6.4 KiB
C
/*
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* QEMU/MIPS pseudo-board
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*
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* emulates a simple machine with ISA-like bus.
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* ISA IO space mapped to the 0x14000000 (PHYS) and
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* ISA memory at the 0x10000000 (PHYS, 16Mb in size).
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* All peripherial devices are attached to this "bus" with
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* the standard PC ISA addresses.
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*/
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#include "vl.h"
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin"
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#else
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#define BIOS_FILENAME "mipsel_bios.bin"
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#endif
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#ifdef MIPS_HAS_MIPS64
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#define INITRD_LOAD_ADDR (int64_t)(int32_t)0x80800000
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#else
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#define INITRD_LOAD_ADDR (int32_t)0x80800000
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#endif
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
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static const int ide_iobase[2] = { 0x1f0, 0x170 };
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static const int ide_iobase2[2] = { 0x3f6, 0x376 };
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static const int ide_irq[2] = { 14, 15 };
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static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
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static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
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extern FILE *logfile;
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static PITState *pit; /* PIT i8254 */
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/*i8254 PIT is attached to the IRQ0 at PIC i8259 */
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/*The PIC is attached to the MIPS CPU INT0 pin */
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static void pic_irq_request(void *opaque, int level)
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{
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cpu_mips_irq_request(opaque, 2, level);
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}
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static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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if ((addr & 0xffff) == 0 && val == 42)
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qemu_system_reset_request ();
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else if ((addr & 0xffff) == 4 && val == 42)
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qemu_system_shutdown_request ();
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}
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static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
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{
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return 0;
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}
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static CPUWriteMemoryFunc *mips_qemu_write[] = {
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&mips_qemu_writel,
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&mips_qemu_writel,
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&mips_qemu_writel,
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};
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static CPUReadMemoryFunc *mips_qemu_read[] = {
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&mips_qemu_readl,
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&mips_qemu_readl,
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&mips_qemu_readl,
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};
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static int mips_qemu_iomemtype = 0;
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void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename)
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{
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int64_t entry = 0;
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long kernel_size, initrd_size;
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kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
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if (kernel_size >= 0) {
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if ((entry & ~0x7fffffffULL) == 0x80000000)
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entry = (int32_t)entry;
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env->PC = entry;
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} else {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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initrd_size = 0;
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if (initrd_filename) {
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initrd_size = load_image(initrd_filename,
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phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
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if (initrd_size == (target_ulong) -1) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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}
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/* Store command line. */
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if (initrd_size > 0) {
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int ret;
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ret = sprintf(phys_ram_base + (16 << 20) - 256,
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"rd_start=0x" TLSZ " rd_size=%li ",
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INITRD_LOAD_ADDR,
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initrd_size);
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strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
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}
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else {
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strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
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}
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*(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
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*(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
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}
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static void main_cpu_reset(void *opaque)
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{
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CPUState *env = opaque;
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cpu_reset(env);
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if (env->kernel_filename)
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load_kernel (env, env->ram_size, env->kernel_filename,
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env->kernel_cmdline, env->initrd_filename);
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}
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void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename)
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{
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char buf[1024];
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unsigned long bios_offset;
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int bios_size;
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CPUState *env;
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static RTCState *rtc_state;
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int i;
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env = cpu_init();
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register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
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qemu_register_reset(main_cpu_reset, env);
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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if (!mips_qemu_iomemtype) {
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mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
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mips_qemu_write, NULL);
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}
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cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
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/* Try to load a BIOS image. If this fails, we continue regardless,
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but initialize the hardware ourselves. When a kernel gets
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preloaded we also initialize the hardware, since the BIOS wasn't
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run. */
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bios_offset = ram_size + vga_ram_size;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
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cpu_register_physical_memory(0x1fc00000,
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BIOS_SIZE, bios_offset | IO_MEM_ROM);
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} else {
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/* not fatal */
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fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
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buf);
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}
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if (kernel_filename) {
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load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
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initrd_filename);
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env->ram_size = ram_size;
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env->kernel_filename = kernel_filename;
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env->kernel_cmdline = kernel_cmdline;
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env->initrd_filename = initrd_filename;
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}
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/* Init CPU internal devices */
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cpu_mips_clock_init(env);
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cpu_mips_irqctrl_init();
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rtc_state = rtc_init(0x70, 8);
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/* Register 64 KB of ISA IO space at 0x14000000 */
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isa_mmio_init(0x14000000, 0x00010000);
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isa_mem_base = 0x10000000;
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isa_pic = pic_init(pic_irq_request, env);
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pit = pit_init(0x40, 0);
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for(i = 0; i < MAX_SERIAL_PORTS; i++) {
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if (serial_hds[i]) {
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serial_init(&pic_set_irq_new, isa_pic,
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serial_io[i], serial_irq[i], serial_hds[i]);
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}
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}
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isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
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vga_ram_size);
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if (nd_table[0].vlan) {
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if (nd_table[0].model == NULL
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|| strcmp(nd_table[0].model, "ne2k_isa") == 0) {
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isa_ne2000_init(0x300, 9, &nd_table[0]);
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} else {
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fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
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exit (1);
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}
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}
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for(i = 0; i < 2; i++)
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isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
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bs_table[2 * i], bs_table[2 * i + 1]);
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}
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QEMUMachine mips_machine = {
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"mips",
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"mips r4k platform",
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mips_r4k_init,
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};
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