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a8170e5e97
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
65 lines
2.5 KiB
C
65 lines
2.5 KiB
C
/*
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* QEMU PowerPC 4xx emulation shared definitions
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if !defined(PPC_4XX_H)
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#define PPC_4XX_H
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#include "pci.h"
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/* PowerPC 4xx core initialization */
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CPUPPCState *ppc4xx_init (const char *cpu_model,
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clk_setup_t *cpu_clk, clk_setup_t *tb_clk,
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uint32_t sysclk);
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/* PowerPC 4xx universal interrupt controller */
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enum {
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PPCUIC_OUTPUT_INT = 0,
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PPCUIC_OUTPUT_CINT = 1,
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PPCUIC_OUTPUT_NB,
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};
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qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs,
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uint32_t dcr_base, int has_ssr, int has_vr);
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ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
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MemoryRegion ram_memories[],
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hwaddr ram_bases[],
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hwaddr ram_sizes[],
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const unsigned int sdram_bank_sizes[]);
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void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks,
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MemoryRegion ram_memories[],
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hwaddr *ram_bases,
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hwaddr *ram_sizes,
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int do_init);
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#define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
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PCIBus *ppc4xx_pci_init(CPUPPCState *env, qemu_irq pci_irqs[4],
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hwaddr config_space,
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hwaddr int_ack,
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hwaddr special_cycle,
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hwaddr registers);
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#endif /* !defined(PPC_4XX_H) */
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