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b950914df3
Currently an object link property is used to pass a reference to the Heathrow PIC into the PCI host bridge so that grackle_init_irqs() can connect the PCI IRQs to the PIC itself. This can be simplified by defining the PCI IRQs as qdev gpios and then wiring up the PCI IRQs to the PIC in the Old World machine init function. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201013114922.2946-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
177 lines
5.6 KiB
C
177 lines
5.6 KiB
C
/*
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* QEMU Grackle PCI host (heathrow OldWorld PowerMac)
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*
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* Copyright (c) 2006-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/pci/pci_host.h"
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#include "hw/ppc/mac.h"
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#include "hw/qdev-properties.h"
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#include "hw/pci/pci.h"
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#include "hw/irq.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qom/object.h"
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OBJECT_DECLARE_SIMPLE_TYPE(GrackleState, GRACKLE_PCI_HOST_BRIDGE)
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struct GrackleState {
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PCIHostState parent_obj;
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uint32_t ofw_addr;
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qemu_irq irqs[4];
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MemoryRegion pci_mmio;
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MemoryRegion pci_hole;
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MemoryRegion pci_io;
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};
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/* Don't know if this matches real hardware, but it agrees with OHW. */
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static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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return (irq_num + (pci_dev->devfn >> 3)) & 3;
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}
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static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
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{
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GrackleState *s = opaque;
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trace_grackle_set_irq(irq_num, level);
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qemu_set_irq(s->irqs[irq_num], level);
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}
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static void grackle_realize(DeviceState *dev, Error **errp)
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{
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GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
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PCIHostState *phb = PCI_HOST_BRIDGE(dev);
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phb->bus = pci_register_root_bus(dev, NULL,
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pci_grackle_set_irq,
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pci_grackle_map_irq,
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s,
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&s->pci_mmio,
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&s->pci_io,
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0, 4, TYPE_PCI_BUS);
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pci_create_simple(phb->bus, 0, "grackle");
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}
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static void grackle_init(Object *obj)
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{
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GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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PCIHostState *phb = PCI_HOST_BRIDGE(obj);
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memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL);
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memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj,
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"pci-isa-mmio", 0x00200000);
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memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio,
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0x80000000ULL, 0x7e000000ULL);
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memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops,
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DEVICE(obj), "pci-conf-idx", 0x1000);
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memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops,
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DEVICE(obj), "pci-data-idx", 0x1000);
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sysbus_init_mmio(sbd, &phb->conf_mem);
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sysbus_init_mmio(sbd, &phb->data_mem);
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sysbus_init_mmio(sbd, &s->pci_hole);
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sysbus_init_mmio(sbd, &s->pci_io);
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qdev_init_gpio_out(DEVICE(obj), s->irqs, ARRAY_SIZE(s->irqs));
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}
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static void grackle_pci_realize(PCIDevice *d, Error **errp)
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{
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d->config[0x09] = 0x01;
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}
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static void grackle_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = grackle_pci_realize;
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k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
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k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106;
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k->revision = 0x00;
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k->class_id = PCI_CLASS_BRIDGE_HOST;
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/*
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* PCI-facing part of the host bridge, not usable without the
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* host-facing part, which can't be device_add'ed, yet.
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*/
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dc->user_creatable = false;
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}
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static const TypeInfo grackle_pci_info = {
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.name = "grackle",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIDevice),
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.class_init = grackle_pci_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static char *grackle_ofw_unit_address(const SysBusDevice *dev)
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{
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GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev);
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return g_strdup_printf("%x", s->ofw_addr);
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}
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static Property grackle_properties[] = {
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DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1),
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DEFINE_PROP_END_OF_LIST()
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};
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static void grackle_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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dc->realize = grackle_realize;
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device_class_set_props(dc, grackle_properties);
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->fw_name = "pci";
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sbc->explicit_ofw_unit_address = grackle_ofw_unit_address;
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}
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static const TypeInfo grackle_host_info = {
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.name = TYPE_GRACKLE_PCI_HOST_BRIDGE,
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.parent = TYPE_PCI_HOST_BRIDGE,
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.instance_size = sizeof(GrackleState),
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.instance_init = grackle_init,
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.class_init = grackle_class_init,
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};
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static void grackle_register_types(void)
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{
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type_register_static(&grackle_pci_info);
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type_register_static(&grackle_host_info);
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}
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type_init(grackle_register_types)
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