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a31768c019
Extend comparison results from mask registers to SEW-width elements, following recommendations in The RISC-V SPEC Volume I (Version 20240411). This aligns with TCG's cmp_vec behavior by expanding compare results to full element width: all 1s for true, all 0s for false. Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241007025700.47259-7-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
25 lines
566 B
C
25 lines
566 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define RISC-V target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('v', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_S12)
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CONST('J', TCG_CT_CONST_J12)
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CONST('K', TCG_CT_CONST_S5)
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CONST('L', TCG_CT_CONST_CMP_VI)
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CONST('N', TCG_CT_CONST_N12)
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CONST('M', TCG_CT_CONST_M12)
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CONST('Z', TCG_CT_CONST_ZERO)
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