TANG Tiancheng 4b7868f8c2 tcg/riscv: Enable native vector support for TCG host ... Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20241007025700.47259-13-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2024-10-22 11:57:25 -07:00
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tcg-target-con-set.h	tcg/riscv: Implement vector shi/s/v ops	2024-10-22 11:57:25 -07:00
tcg-target-con-str.h	tcg/riscv: Implement vector cmp/cmpsel ops	2024-10-22 11:57:25 -07:00
tcg-target-reg-bits.h	tcg: Split out tcg-target-reg-bits.h	2023-06-05 12:04:28 -07:00
tcg-target.c.inc	tcg/riscv: Implement vector roti/v/x ops	2024-10-22 11:57:25 -07:00
tcg-target.h	tcg/riscv: Enable native vector support for TCG host	2024-10-22 11:57:25 -07:00
tcg-target.opc.h	tcg/riscv: Add basic support for vector	2024-10-22 11:57:25 -07:00