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8f3ae2ae2d
Support guest CPUs which need 7 MMU index values. Add a comment about what would be required to raise the limit further (trivial for 8, TCG backend rework for 9 or more). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
365 lines
9.2 KiB
C
365 lines
9.2 KiB
C
/*
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* Software MMU support
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Generate inline load/store functions for all MMU modes (typically
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* at least _user and _kernel) as well as _data versions, for all data
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* sizes.
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*
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* Used by target op helpers.
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*
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* The syntax for the accessors is:
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*
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* load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
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*
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* store: cpu_st{sign}{size}_{mmusuffix}(env, ptr, val)
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*
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* sign is:
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* (empty): for 32 and 64 bit sizes
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* mmusuffix is one of the generic suffixes "data" or "code", or
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* (for softmmu configs) a target-specific MMU mode suffix as defined
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* in target cpu.h.
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*/
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#ifndef CPU_LDST_H
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#define CPU_LDST_H
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#if defined(CONFIG_USER_ONLY)
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/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
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#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
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#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
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#define h2g_valid(x) 1
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#else
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#define h2g_valid(x) ({ \
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unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
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(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
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(!RESERVED_VA || (__guest < RESERVED_VA)); \
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})
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#endif
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#define h2g_nocheck(x) ({ \
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unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
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(abi_ulong)__ret; \
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})
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#define h2g(x) ({ \
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/* Check if given address fits target address space */ \
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assert(h2g_valid(x)); \
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h2g_nocheck(x); \
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})
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#endif
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#if defined(CONFIG_USER_ONLY)
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/* In user-only mode we provide only the _code and _data accessors. */
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#define MEMSUFFIX _data
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_useronly_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_useronly_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_useronly_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_useronly_template.h"
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#undef MEMSUFFIX
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#define MEMSUFFIX _code
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#define CODE_ACCESS
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_useronly_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_useronly_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_useronly_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_useronly_template.h"
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#undef MEMSUFFIX
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#undef CODE_ACCESS
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#else
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/* The memory helpers for tcg-generated code need tcg_target_long etc. */
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#include "tcg.h"
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uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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void helper_stb_mmu(CPUArchState *env, target_ulong addr,
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uint8_t val, int mmu_idx);
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void helper_stw_mmu(CPUArchState *env, target_ulong addr,
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uint16_t val, int mmu_idx);
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void helper_stl_mmu(CPUArchState *env, target_ulong addr,
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uint32_t val, int mmu_idx);
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void helper_stq_mmu(CPUArchState *env, target_ulong addr,
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uint64_t val, int mmu_idx);
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uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
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#ifdef MMU_MODE0_SUFFIX
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#define CPU_MMU_INDEX 0
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#define MEMSUFFIX MMU_MODE0_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif
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#if (NB_MMU_MODES >= 2) && defined(MMU_MODE1_SUFFIX)
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#define CPU_MMU_INDEX 1
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#define MEMSUFFIX MMU_MODE1_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif
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#if (NB_MMU_MODES >= 3) && defined(MMU_MODE2_SUFFIX)
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#define CPU_MMU_INDEX 2
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#define MEMSUFFIX MMU_MODE2_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 3) */
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#if (NB_MMU_MODES >= 4) && defined(MMU_MODE3_SUFFIX)
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#define CPU_MMU_INDEX 3
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#define MEMSUFFIX MMU_MODE3_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 4) */
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#if (NB_MMU_MODES >= 5) && defined(MMU_MODE4_SUFFIX)
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#define CPU_MMU_INDEX 4
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#define MEMSUFFIX MMU_MODE4_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 5) */
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#if (NB_MMU_MODES >= 6) && defined(MMU_MODE5_SUFFIX)
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#define CPU_MMU_INDEX 5
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#define MEMSUFFIX MMU_MODE5_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 6) */
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#if (NB_MMU_MODES >= 7) && defined(MMU_MODE6_SUFFIX)
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#define CPU_MMU_INDEX 6
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#define MEMSUFFIX MMU_MODE6_SUFFIX
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#endif /* (NB_MMU_MODES >= 7) */
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#if (NB_MMU_MODES > 7)
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/* Note that supporting NB_MMU_MODES == 9 would require
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* changes to at least the ARM TCG backend.
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*/
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#error "NB_MMU_MODES > 7 is not supported for now"
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#endif /* (NB_MMU_MODES > 7) */
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/* these access are slower, they must be as rare as possible */
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#define CPU_MMU_INDEX (cpu_mmu_index(env))
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#define MEMSUFFIX _data
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#define CPU_MMU_INDEX (cpu_mmu_index(env))
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#define MEMSUFFIX _code
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#define SOFTMMU_CODE_ACCESS
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#define DATA_SIZE 1
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 2
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 4
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#include "exec/cpu_ldst_template.h"
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#define DATA_SIZE 8
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#include "exec/cpu_ldst_template.h"
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#undef CPU_MMU_INDEX
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#undef MEMSUFFIX
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#undef SOFTMMU_CODE_ACCESS
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/**
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* tlb_vaddr_to_host:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If the TLB contains a host virtual address suitable for direct RAM
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* access, then return it. Otherwise (TLB miss, TLB entry is for an
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* I/O access, etc) return NULL.
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*
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* This is the equivalent of the initial fast-path code used by
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* TCG backends for guest load and store accesses.
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*/
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static inline void *tlb_vaddr_to_host(CPUArchState *env, target_ulong addr,
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int access_type, int mmu_idx)
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{
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int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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CPUTLBEntry *tlbentry = &env->tlb_table[mmu_idx][index];
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target_ulong tlb_addr;
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uintptr_t haddr;
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switch (access_type) {
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case 0:
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tlb_addr = tlbentry->addr_read;
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break;
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case 1:
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tlb_addr = tlbentry->addr_write;
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break;
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case 2:
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tlb_addr = tlbentry->addr_code;
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break;
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default:
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g_assert_not_reached();
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}
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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/* TLB entry is for a different page */
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return NULL;
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}
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if (tlb_addr & ~TARGET_PAGE_MASK) {
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/* IO access */
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return NULL;
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}
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haddr = addr + env->tlb_table[mmu_idx][index].addend;
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return (void *)haddr;
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}
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#endif /* defined(CONFIG_USER_ONLY) */
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#endif /* CPU_LDST_H */
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