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ed2803da58
Prepares for changing cpu_single_step() argument to CPUState. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Signed-off-by: Andreas Färber <afaerber@suse.de>
930 lines
29 KiB
C
930 lines
29 KiB
C
/*
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* Moxie emulation for qemu: main translation routines.
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*
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* Copyright (c) 2009, 2013 Anthony Green
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License
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* as published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* For information on the Moxie architecture, see
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* http://moxielogic.org/wiki
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <assert.h>
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "disas/disas.h"
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#include "tcg-op.h"
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#include "helper.h"
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#define GEN_HELPER 1
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#include "helper.h"
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/* This is the state at translation time. */
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typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc, saved_pc;
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uint32_t opcode;
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uint32_t fp_status;
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/* Routine used to access memory */
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int memidx;
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int bstate;
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target_ulong btarget;
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int singlestep_enabled;
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} DisasContext;
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enum {
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BS_NONE = 0, /* We go out of the TB without reaching a branch or an
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* exception condition */
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BS_STOP = 1, /* We want to stop translation for any reason */
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BS_BRANCH = 2, /* We reached a branch condition */
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BS_EXCP = 3, /* We reached an exception condition */
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};
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static TCGv cpu_pc;
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static TCGv cpu_gregs[16];
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static TCGv_ptr cpu_env;
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static TCGv cc_a, cc_b;
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#include "exec/gen-icount.h"
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#define REG(x) (cpu_gregs[x])
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/* Extract the signed 10-bit offset from a 16-bit branch
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instruction. */
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static int extract_branch_offset(int opcode)
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{
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return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
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}
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void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
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int flags)
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{
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MoxieCPU *cpu = MOXIE_CPU(cs);
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CPUMoxieState *env = &cpu->env;
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int i;
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cpu_fprintf(f, "pc=0x%08x\n", env->pc);
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cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
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env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
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for (i = 4; i < 16; i += 4) {
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cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
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i-2, env->gregs[i], i-1, env->gregs[i + 1],
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i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
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}
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for (i = 4; i < 16; i += 4) {
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cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
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i-2, env->sregs[i], i-1, env->sregs[i + 1],
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i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
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}
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}
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void moxie_translate_init(void)
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{
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int i;
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static int done_init;
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static const char * const gregnames[16] = {
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"$fp", "$sp", "$r0", "$r1",
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"$r2", "$r3", "$r4", "$r5",
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"$r6", "$r7", "$r8", "$r9",
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"$r10", "$r11", "$r12", "$r13"
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};
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if (done_init) {
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return;
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}
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUMoxieState, pc), "$pc");
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for (i = 0; i < 16; i++)
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cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUMoxieState, gregs[i]),
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gregnames[i]);
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cc_a = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUMoxieState, cc_a), "cc_a");
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cc_b = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUMoxieState, cc_b), "cc_b");
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done_init = 1;
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}
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static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
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int n, target_ulong dest)
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{
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TranslationBlock *tb;
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tb = ctx->tb;
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if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
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!ctx->singlestep_enabled) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_i32(cpu_pc, dest);
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tcg_gen_exit_tb((tcg_target_long)tb + n);
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} else {
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tcg_gen_movi_i32(cpu_pc, dest);
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if (ctx->singlestep_enabled) {
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gen_helper_debug(cpu_env);
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}
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tcg_gen_exit_tb(0);
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}
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}
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static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
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{
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CPUMoxieState *env = &cpu->env;
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/* Local cache for the instruction opcode. */
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int opcode;
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/* Set the default instruction length. */
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int length = 2;
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if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
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tcg_gen_debug_insn_start(ctx->pc);
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}
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/* Examine the 16-bit opcode. */
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opcode = ctx->opcode;
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/* Decode instruction. */
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if (opcode & (1 << 15)) {
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if (opcode & (1 << 14)) {
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/* This is a Form 3 instruction. */
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int inst = (opcode >> 10 & 0xf);
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#define BRANCH(cond) \
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do { \
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int l1 = gen_new_label(); \
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tcg_gen_brcond_i32(cond, cc_a, cc_b, l1); \
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gen_goto_tb(env, ctx, 1, ctx->pc+2); \
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gen_set_label(l1); \
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gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
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ctx->bstate = BS_BRANCH; \
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} while (0)
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switch (inst) {
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case 0x00: /* beq */
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BRANCH(TCG_COND_EQ);
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break;
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case 0x01: /* bne */
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BRANCH(TCG_COND_NE);
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break;
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case 0x02: /* blt */
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BRANCH(TCG_COND_LT);
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break;
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case 0x03: /* bgt */
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BRANCH(TCG_COND_GT);
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break;
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case 0x04: /* bltu */
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BRANCH(TCG_COND_LTU);
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break;
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case 0x05: /* bgtu */
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BRANCH(TCG_COND_GTU);
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break;
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case 0x06: /* bge */
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BRANCH(TCG_COND_GE);
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break;
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case 0x07: /* ble */
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BRANCH(TCG_COND_LE);
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break;
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case 0x08: /* bgeu */
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BRANCH(TCG_COND_GEU);
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break;
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case 0x09: /* bleu */
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BRANCH(TCG_COND_LEU);
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break;
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default:
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{
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TCGv temp = tcg_temp_new_i32();
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tcg_gen_movi_i32(cpu_pc, ctx->pc);
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tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
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gen_helper_raise_exception(cpu_env, temp);
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tcg_temp_free_i32(temp);
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}
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break;
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}
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} else {
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/* This is a Form 2 instruction. */
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int inst = (opcode >> 12 & 0x3);
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switch (inst) {
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case 0x00: /* inc */
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{
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int a = (opcode >> 8) & 0xf;
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unsigned int v = (opcode & 0xff);
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tcg_gen_addi_i32(REG(a), REG(a), v);
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}
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break;
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case 0x01: /* dec */
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{
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int a = (opcode >> 8) & 0xf;
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unsigned int v = (opcode & 0xff);
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tcg_gen_subi_i32(REG(a), REG(a), v);
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}
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break;
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case 0x02: /* gsr */
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{
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int a = (opcode >> 8) & 0xf;
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unsigned v = (opcode & 0xff);
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tcg_gen_ld_i32(REG(a), cpu_env,
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offsetof(CPUMoxieState, sregs[v]));
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}
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break;
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case 0x03: /* ssr */
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{
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int a = (opcode >> 8) & 0xf;
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unsigned v = (opcode & 0xff);
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tcg_gen_st_i32(REG(a), cpu_env,
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offsetof(CPUMoxieState, sregs[v]));
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}
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break;
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default:
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{
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TCGv temp = tcg_temp_new_i32();
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tcg_gen_movi_i32(cpu_pc, ctx->pc);
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tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
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gen_helper_raise_exception(cpu_env, temp);
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tcg_temp_free_i32(temp);
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}
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break;
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}
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}
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} else {
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/* This is a Form 1 instruction. */
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int inst = opcode >> 8;
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switch (inst) {
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case 0x00: /* nop */
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break;
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case 0x01: /* ldi.l (immediate) */
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{
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int reg = (opcode >> 4) & 0xf;
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int val = cpu_ldl_code(env, ctx->pc+2);
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tcg_gen_movi_i32(REG(reg), val);
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length = 6;
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}
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break;
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case 0x02: /* mov (register-to-register) */
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{
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int dest = (opcode >> 4) & 0xf;
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int src = opcode & 0xf;
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tcg_gen_mov_i32(REG(dest), REG(src));
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}
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break;
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case 0x03: /* jsra */
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{
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TCGv t1 = tcg_temp_new_i32();
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TCGv t2 = tcg_temp_new_i32();
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tcg_gen_movi_i32(t1, ctx->pc + 6);
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/* Make space for the static chain and return address. */
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tcg_gen_subi_i32(t2, REG(1), 8);
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tcg_gen_mov_i32(REG(1), t2);
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tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
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/* Push the current frame pointer. */
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tcg_gen_subi_i32(t2, REG(1), 4);
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tcg_gen_mov_i32(REG(1), t2);
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tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
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/* Set the pc and $fp. */
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tcg_gen_mov_i32(REG(0), REG(1));
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gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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ctx->bstate = BS_BRANCH;
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length = 6;
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}
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break;
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case 0x04: /* ret */
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{
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TCGv t1 = tcg_temp_new_i32();
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/* The new $sp is the old $fp. */
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tcg_gen_mov_i32(REG(1), REG(0));
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/* Pop the frame pointer. */
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tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
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tcg_gen_addi_i32(t1, REG(1), 4);
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tcg_gen_mov_i32(REG(1), t1);
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/* Pop the return address and skip over the static chain
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slot. */
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tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
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tcg_gen_addi_i32(t1, REG(1), 8);
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tcg_gen_mov_i32(REG(1), t1);
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tcg_temp_free_i32(t1);
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/* Jump... */
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tcg_gen_exit_tb(0);
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ctx->bstate = BS_BRANCH;
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}
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break;
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case 0x05: /* add.l */
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{
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int a = (opcode >> 4) & 0xf;
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int b = opcode & 0xf;
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tcg_gen_add_i32(REG(a), REG(a), REG(b));
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}
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break;
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case 0x06: /* push */
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{
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int a = (opcode >> 4) & 0xf;
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int b = opcode & 0xf;
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TCGv t1 = tcg_temp_new_i32();
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tcg_gen_subi_i32(t1, REG(a), 4);
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tcg_gen_mov_i32(REG(a), t1);
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tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
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tcg_temp_free_i32(t1);
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}
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break;
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case 0x07: /* pop */
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{
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int a = (opcode >> 4) & 0xf;
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int b = opcode & 0xf;
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TCGv t1 = tcg_temp_new_i32();
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tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
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tcg_gen_addi_i32(t1, REG(a), 4);
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tcg_gen_mov_i32(REG(a), t1);
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tcg_temp_free_i32(t1);
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}
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break;
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case 0x08: /* lda.l */
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{
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int reg = (opcode >> 4) & 0xf;
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TCGv ptr = tcg_temp_new_i32();
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tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
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tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
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tcg_temp_free_i32(ptr);
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length = 6;
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}
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break;
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case 0x09: /* sta.l */
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{
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int val = (opcode >> 4) & 0xf;
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TCGv ptr = tcg_temp_new_i32();
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tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
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tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
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tcg_temp_free_i32(ptr);
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length = 6;
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}
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break;
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case 0x0a: /* ld.l (register indirect) */
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{
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int src = opcode & 0xf;
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int dest = (opcode >> 4) & 0xf;
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tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
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}
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break;
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case 0x0b: /* st.l */
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{
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int dest = (opcode >> 4) & 0xf;
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int val = opcode & 0xf;
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tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
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}
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break;
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case 0x0c: /* ldo.l */
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{
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int a = (opcode >> 4) & 0xf;
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int b = opcode & 0xf;
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TCGv t1 = tcg_temp_new_i32();
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TCGv t2 = tcg_temp_new_i32();
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tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
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tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
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tcg_gen_mov_i32(REG(a), t2);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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length = 6;
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}
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break;
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case 0x0d: /* sto.l */
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{
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int a = (opcode >> 4) & 0xf;
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int b = opcode & 0xf;
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TCGv t1 = tcg_temp_new_i32();
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TCGv t2 = tcg_temp_new_i32();
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tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
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tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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length = 6;
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}
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break;
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case 0x0e: /* cmp */
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{
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int a = (opcode >> 4) & 0xf;
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int b = opcode & 0xf;
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tcg_gen_mov_i32(cc_a, REG(a));
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tcg_gen_mov_i32(cc_b, REG(b));
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}
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break;
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case 0x19: /* jsr */
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{
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int fnreg = (opcode >> 4) & 0xf;
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/* Load the stack pointer into T0. */
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TCGv t1 = tcg_temp_new_i32();
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TCGv t2 = tcg_temp_new_i32();
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tcg_gen_movi_i32(t1, ctx->pc+2);
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/* Make space for the static chain and return address. */
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tcg_gen_subi_i32(t2, REG(1), 8);
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tcg_gen_mov_i32(REG(1), t2);
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tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
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/* Push the current frame pointer. */
|
|
tcg_gen_subi_i32(t2, REG(1), 4);
|
|
tcg_gen_mov_i32(REG(1), t2);
|
|
tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
|
|
|
|
/* Set the pc and $fp. */
|
|
tcg_gen_mov_i32(REG(0), REG(1));
|
|
tcg_gen_mov_i32(cpu_pc, REG(fnreg));
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t2);
|
|
tcg_gen_exit_tb(0);
|
|
ctx->bstate = BS_BRANCH;
|
|
}
|
|
break;
|
|
case 0x1a: /* jmpa */
|
|
{
|
|
tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_exit_tb(0);
|
|
ctx->bstate = BS_BRANCH;
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x1b: /* ldi.b (immediate) */
|
|
{
|
|
int reg = (opcode >> 4) & 0xf;
|
|
int val = cpu_ldl_code(env, ctx->pc+2);
|
|
tcg_gen_movi_i32(REG(reg), val);
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x1c: /* ld.b (register indirect) */
|
|
{
|
|
int src = opcode & 0xf;
|
|
int dest = (opcode >> 4) & 0xf;
|
|
|
|
tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
|
|
}
|
|
break;
|
|
case 0x1d: /* lda.b */
|
|
{
|
|
int reg = (opcode >> 4) & 0xf;
|
|
|
|
TCGv ptr = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
|
|
tcg_temp_free_i32(ptr);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x1e: /* st.b */
|
|
{
|
|
int dest = (opcode >> 4) & 0xf;
|
|
int val = opcode & 0xf;
|
|
|
|
tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
|
|
}
|
|
break;
|
|
case 0x1f: /* sta.b */
|
|
{
|
|
int val = (opcode >> 4) & 0xf;
|
|
|
|
TCGv ptr = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
|
|
tcg_temp_free_i32(ptr);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x20: /* ldi.s (immediate) */
|
|
{
|
|
int reg = (opcode >> 4) & 0xf;
|
|
int val = cpu_ldl_code(env, ctx->pc+2);
|
|
tcg_gen_movi_i32(REG(reg), val);
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x21: /* ld.s (register indirect) */
|
|
{
|
|
int src = opcode & 0xf;
|
|
int dest = (opcode >> 4) & 0xf;
|
|
|
|
tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
|
|
}
|
|
break;
|
|
case 0x22: /* lda.s */
|
|
{
|
|
int reg = (opcode >> 4) & 0xf;
|
|
|
|
TCGv ptr = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
|
|
tcg_temp_free_i32(ptr);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x23: /* st.s */
|
|
{
|
|
int dest = (opcode >> 4) & 0xf;
|
|
int val = opcode & 0xf;
|
|
|
|
tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
|
|
}
|
|
break;
|
|
case 0x24: /* sta.s */
|
|
{
|
|
int val = (opcode >> 4) & 0xf;
|
|
|
|
TCGv ptr = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
|
|
tcg_temp_free_i32(ptr);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x25: /* jmp */
|
|
{
|
|
int reg = (opcode >> 4) & 0xf;
|
|
tcg_gen_mov_i32(cpu_pc, REG(reg));
|
|
tcg_gen_exit_tb(0);
|
|
ctx->bstate = BS_BRANCH;
|
|
}
|
|
break;
|
|
case 0x26: /* and */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_and_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x27: /* lshr */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv sv = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(sv, REG(b), 0x1f);
|
|
tcg_gen_shr_i32(REG(a), REG(a), sv);
|
|
tcg_temp_free_i32(sv);
|
|
}
|
|
break;
|
|
case 0x28: /* ashl */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv sv = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(sv, REG(b), 0x1f);
|
|
tcg_gen_shl_i32(REG(a), REG(a), sv);
|
|
tcg_temp_free_i32(sv);
|
|
}
|
|
break;
|
|
case 0x29: /* sub.l */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_sub_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x2a: /* neg */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_neg_i32(REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x2b: /* or */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_or_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x2c: /* not */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_not_i32(REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x2d: /* ashr */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv sv = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(sv, REG(b), 0x1f);
|
|
tcg_gen_sar_i32(REG(a), REG(a), sv);
|
|
tcg_temp_free_i32(sv);
|
|
}
|
|
break;
|
|
case 0x2e: /* xor */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_xor_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x2f: /* mul.l */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
tcg_gen_mul_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x30: /* swi */
|
|
{
|
|
int val = cpu_ldl_code(env, ctx->pc+2);
|
|
|
|
TCGv temp = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(temp, val);
|
|
tcg_gen_st_i32(temp, cpu_env,
|
|
offsetof(CPUMoxieState, sregs[3]));
|
|
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
|
tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
|
|
gen_helper_raise_exception(cpu_env, temp);
|
|
tcg_temp_free_i32(temp);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x31: /* div.l */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
|
gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x32: /* udiv.l */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
|
gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x33: /* mod.l */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
tcg_gen_rem_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x34: /* umod.l */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
tcg_gen_remu_i32(REG(a), REG(a), REG(b));
|
|
}
|
|
break;
|
|
case 0x35: /* brk */
|
|
{
|
|
TCGv temp = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
|
tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
|
|
gen_helper_raise_exception(cpu_env, temp);
|
|
tcg_temp_free_i32(temp);
|
|
}
|
|
break;
|
|
case 0x36: /* ldo.b */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv t1 = tcg_temp_new_i32();
|
|
TCGv t2 = tcg_temp_new_i32();
|
|
tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
|
|
tcg_gen_mov_i32(REG(a), t2);
|
|
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t2);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x37: /* sto.b */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv t1 = tcg_temp_new_i32();
|
|
TCGv t2 = tcg_temp_new_i32();
|
|
tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
|
|
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t2);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x38: /* ldo.s */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv t1 = tcg_temp_new_i32();
|
|
TCGv t2 = tcg_temp_new_i32();
|
|
tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
|
|
tcg_gen_mov_i32(REG(a), t2);
|
|
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t2);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
case 0x39: /* sto.s */
|
|
{
|
|
int a = (opcode >> 4) & 0xf;
|
|
int b = opcode & 0xf;
|
|
|
|
TCGv t1 = tcg_temp_new_i32();
|
|
TCGv t2 = tcg_temp_new_i32();
|
|
tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
|
|
tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
|
|
tcg_temp_free_i32(t1);
|
|
tcg_temp_free_i32(t2);
|
|
|
|
length = 6;
|
|
}
|
|
break;
|
|
default:
|
|
{
|
|
TCGv temp = tcg_temp_new_i32();
|
|
tcg_gen_movi_i32(cpu_pc, ctx->pc);
|
|
tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
|
|
gen_helper_raise_exception(cpu_env, temp);
|
|
tcg_temp_free_i32(temp);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
return length;
|
|
}
|
|
|
|
/* generate intermediate code for basic block 'tb'. */
|
|
static inline void
|
|
gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
|
|
bool search_pc)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
DisasContext ctx;
|
|
target_ulong pc_start;
|
|
uint16_t *gen_opc_end;
|
|
CPUBreakpoint *bp;
|
|
int j, lj = -1;
|
|
CPUMoxieState *env = &cpu->env;
|
|
int num_insns;
|
|
|
|
pc_start = tb->pc;
|
|
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
|
ctx.pc = pc_start;
|
|
ctx.saved_pc = -1;
|
|
ctx.tb = tb;
|
|
ctx.memidx = 0;
|
|
ctx.singlestep_enabled = 0;
|
|
ctx.bstate = BS_NONE;
|
|
num_insns = 0;
|
|
|
|
gen_tb_start();
|
|
do {
|
|
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
|
if (ctx.pc == bp->pc) {
|
|
tcg_gen_movi_i32(cpu_pc, ctx.pc);
|
|
gen_helper_debug(cpu_env);
|
|
ctx.bstate = BS_EXCP;
|
|
goto done_generating;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (search_pc) {
|
|
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
|
|
if (lj < j) {
|
|
lj++;
|
|
while (lj < j) {
|
|
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
}
|
|
tcg_ctx.gen_opc_pc[lj] = ctx.pc;
|
|
tcg_ctx.gen_opc_instr_start[lj] = 1;
|
|
tcg_ctx.gen_opc_icount[lj] = num_insns;
|
|
}
|
|
ctx.opcode = cpu_lduw_code(env, ctx.pc);
|
|
ctx.pc += decode_opc(cpu, &ctx);
|
|
num_insns++;
|
|
|
|
if (cs->singlestep_enabled) {
|
|
break;
|
|
}
|
|
|
|
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
|
|
break;
|
|
}
|
|
} while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end);
|
|
|
|
if (cs->singlestep_enabled) {
|
|
tcg_gen_movi_tl(cpu_pc, ctx.pc);
|
|
gen_helper_debug(cpu_env);
|
|
} else {
|
|
switch (ctx.bstate) {
|
|
case BS_STOP:
|
|
case BS_NONE:
|
|
gen_goto_tb(env, &ctx, 0, ctx.pc);
|
|
break;
|
|
case BS_EXCP:
|
|
tcg_gen_exit_tb(0);
|
|
break;
|
|
case BS_BRANCH:
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
done_generating:
|
|
gen_tb_end(tb, num_insns);
|
|
*tcg_ctx.gen_opc_ptr = INDEX_op_end;
|
|
if (search_pc) {
|
|
j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
|
|
lj++;
|
|
while (lj <= j) {
|
|
tcg_ctx.gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
} else {
|
|
tb->size = ctx.pc - pc_start;
|
|
tb->icount = num_insns;
|
|
}
|
|
}
|
|
|
|
void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, false);
|
|
}
|
|
|
|
void gen_intermediate_code_pc(CPUMoxieState *env, struct TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(moxie_env_get_cpu(env), tb, true);
|
|
}
|
|
|
|
void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb, int pc_pos)
|
|
{
|
|
env->pc = tcg_ctx.gen_opc_pc[pc_pos];
|
|
}
|