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152ef803ce
During boot, PAPR guests negotiate CPU model support with the
ibm,client-architecture-support mechanism. The logic to implement this in
qemu is very convoluted. This cleans it up to be cleaner, using the new
ppc_check_compat() call.
The new logic for choosing a compatibility mode is:
1. Usually, use the most recent compatibility mode that is
a) supported by the guest
b) supported by the CPU
and c) no later than the maximum allowed (if specified)
2. If no suitable compatibility mode was found, the guest *does*
support this CPU explicitly, and no maximum compatibility mode is
specified, then use "raw" mode for the current CPU
3. Otherwise, fail the boot.
This differs from the results of the old code: the old code preferred using
"raw" mode to a compatibility mode, whereas the new code prefers a
compatibility mode if available. Using compatibility mode preferentially
means that we're more likely to be able to migrate the guest to a similar
but not identical host.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
88 lines
6.5 KiB
Plaintext
88 lines
6.5 KiB
Plaintext
# See docs/tracing.txt for syntax documentation.
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# hw/ppc/spapr_pci.c
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spapr_pci_msi(const char *msg, uint32_t ca) "%s (cfg=%x)"
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spapr_pci_msi_setup(const char *name, unsigned vector, uint64_t addr) "dev\"%s\" vector %u, addr=%"PRIx64
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spapr_pci_rtas_ibm_change_msi(unsigned cfg, unsigned func, unsigned req, unsigned first) "cfgaddr %x func %u, requested %u, first irq %u"
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spapr_pci_rtas_ibm_query_interrupt_source_number(unsigned ioa, unsigned intr) "queries for #%u, IRQ%u"
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spapr_pci_msi_write(uint64_t addr, uint64_t data, uint32_t dt_irq) "@%"PRIx64"<=%"PRIx64" IRQ %u"
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spapr_pci_lsi_set(const char *busname, int pin, uint32_t irq) "%s PIN%d IRQ %u"
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spapr_pci_msi_retry(unsigned config_addr, unsigned req_num, unsigned max_irqs) "Guest device at %x asked %u, have only %u"
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# hw/ppc/spapr.c
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spapr_cas_failed(unsigned long n) "DT diff buffer is too small: %ld bytes"
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spapr_cas_continue(unsigned long n) "Copy changes to the guest: %ld bytes"
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# hw/ppc/spapr_hcall.c
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spapr_cas_pvr_try(uint32_t pvr) "%x"
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spapr_cas_pvr(uint32_t cur_pvr, bool explicit_match, uint32_t new_pvr) "current=%x, explicit_match=%u, new=%x"
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# hw/ppc/spapr_iommu.c
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spapr_iommu_put(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tce=0x%"PRIx64" ret=%"PRId64
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spapr_iommu_get(uint64_t liobn, uint64_t ioba, uint64_t ret, uint64_t tce) "liobn=%"PRIx64" ioba=0x%"PRIx64" ret=%"PRId64" tce=0x%"PRIx64
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spapr_iommu_indirect(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t iobaN, uint64_t tceN, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tcelist=0x%"PRIx64" iobaN=0x%"PRIx64" tceN=0x%"PRIx64" ret=%"PRId64
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spapr_iommu_stuff(uint64_t liobn, uint64_t ioba, uint64_t tce_value, uint64_t npages, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tcevalue=0x%"PRIx64" npages=%"PRId64" ret=%"PRId64
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spapr_iommu_pci_put(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tce=0x%"PRIx64" ret=%"PRId64
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spapr_iommu_pci_get(uint64_t liobn, uint64_t ioba, uint64_t ret, uint64_t tce) "liobn=%"PRIx64" ioba=0x%"PRIx64" ret=%"PRId64" tce=0x%"PRIx64
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spapr_iommu_pci_indirect(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t iobaN, uint64_t tceN, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tcelist=0x%"PRIx64" iobaN=0x%"PRIx64" tceN=0x%"PRIx64" ret=%"PRId64
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spapr_iommu_pci_stuff(uint64_t liobn, uint64_t ioba, uint64_t tce_value, uint64_t npages, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tcevalue=0x%"PRIx64" npages=%"PRId64" ret=%"PRId64
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spapr_iommu_xlate(uint64_t liobn, uint64_t ioba, uint64_t tce, unsigned perm, unsigned pgsize) "liobn=%"PRIx64" 0x%"PRIx64" -> 0x%"PRIx64" perm=%u mask=%x"
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spapr_iommu_new_table(uint64_t liobn, void *table, int fd) "liobn=%"PRIx64" table=%p fd=%d"
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spapr_iommu_pre_save(uint64_t liobn, uint32_t nb, uint64_t offs, uint32_t ps) "liobn=%"PRIx64" %"PRIx32" bus_offset=%"PRIx64" ps=%"PRIu32
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spapr_iommu_post_load(uint64_t liobn, uint32_t pre_nb, uint32_t post_nb, uint64_t offs, uint32_t ps) "liobn=%"PRIx64" %"PRIx32" => %"PRIx32" bus_offset=%"PRIx64" ps=%"PRIu32
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spapr_iommu_ddw_query(uint64_t buid, uint32_t cfgaddr, unsigned wa, uint64_t win_size, uint32_t pgmask) "buid=%"PRIx64" addr=%"PRIx32", %u windows available, max window size=%"PRIx64", mask=%"PRIx32
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spapr_iommu_ddw_create(uint64_t buid, uint32_t cfgaddr, uint64_t pg_size, uint64_t req_size, uint64_t start, uint32_t liobn) "buid=%"PRIx64" addr=%"PRIx32", page size=0x%"PRIx64", requested=0x%"PRIx64", start addr=%"PRIx64", liobn=%"PRIx32
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spapr_iommu_ddw_remove(uint32_t liobn) "liobn=%"PRIx32
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spapr_iommu_ddw_reset(uint64_t buid, uint32_t cfgaddr) "buid=%"PRIx64" addr=%"PRIx32
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# hw/ppc/spapr_drc.c
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spapr_drc_set_isolation_state(uint32_t index, int state) "drc: 0x%"PRIx32", state: %"PRIx32
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spapr_drc_set_isolation_state_finalizing(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_set_isolation_state_deferring(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_set_indicator_state(uint32_t index, int state) "drc: 0x%"PRIx32", state: 0x%x"
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spapr_drc_set_allocation_state(uint32_t index, int state) "drc: 0x%"PRIx32", state: 0x%x"
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spapr_drc_set_allocation_state_finalizing(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_set_configured(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_set_configured_skipping(uint32_t index) "drc: 0x%"PRIx32", isolated device"
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spapr_drc_entity_sense(uint32_t index, int state) "drc: 0x%"PRIx32", state: 0x%x"
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spapr_drc_attach(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_detach(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_awaiting_isolated(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_awaiting_unusable(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_awaiting_allocation(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_reset(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_realize(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_realize_child(uint32_t index, char *childname) "drc: 0x%"PRIx32", child name: %s"
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spapr_drc_realize_complete(uint32_t index) "drc: 0x%"PRIx32
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spapr_drc_unrealize(uint32_t index) "drc: 0x%"PRIx32
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# hw/ppc/spapr_rtas.c
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spapr_rtas_set_indicator_invalid(uint32_t index) "sensor index: 0x%"PRIx32
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spapr_rtas_set_indicator_not_supported(uint32_t index, uint32_t type) "sensor index: 0x%"PRIx32", type: %"PRIu32
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spapr_rtas_get_sensor_state_not_supported(uint32_t index, uint32_t type) "sensor index: 0x%"PRIx32", type: %"PRIu32
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spapr_rtas_get_sensor_state_invalid(uint32_t index) "sensor index: 0x%"PRIx32
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spapr_rtas_ibm_configure_connector_invalid(uint32_t index) "DRC index: 0x%"PRIx32
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spapr_rtas_ibm_configure_connector_missing_fdt(uint32_t index) "DRC index: 0x%"PRIx32
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# hw/ppc/spapr_vio.c
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spapr_vio_h_reg_crq(uint64_t reg, uint64_t queue_addr, uint64_t queue_len) "CRQ for dev 0x%" PRIx64 " registered at 0x%" PRIx64 "/0x%" PRIx64
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spapr_vio_free_crq(uint32_t reg) "CRQ for dev 0x%" PRIx32 " freed"
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# hw/ppc/ppc.c
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ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "adjusted from 0x%"PRIx64" to 0x%"PRIx64", diff %"PRId64" (%"PRId64"s)"
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# hw/ppc/prep.c
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prep_io_800_writeb(uint32_t addr, uint32_t val) "0x%08" PRIx32 " => 0x%02" PRIx32
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prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRIx32
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# hw/ppc/prep_systemio.c
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prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
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prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
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# hw/ppc/rs6000_mc.c
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rs6000mc_id_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
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rs6000mc_presence_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
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rs6000mc_size_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
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rs6000mc_size_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
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rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
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