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765fdc1e83
The architecture specification calls for the EPCR to be set to "Address
of next not executed instruction" when there is a floating point
exception (FPE). This was not being done, so fix it by using the same
pattern as syscall. Also, we move this logic down to be done for
instructions not in the delay slot as called for by the architecture
manual.
Without this patch FPU exceptions will loop, as the exception handling
will always return back to the failed floating point instruction.
This was not noticed in earlier testing because:
1. The compiler usually generates code which clobbers the input operand
such as:
lf.div.s r19,r17,r19
2. The target will store the operation output before to the register
before handling the exception. So an operation such as:
float a = 100.0f;
float b = 0.0f;
float c = a / b; /* lf.div.s r19,r17,r19 */
Will first execute:
100 / 0 -> Store inf to c (r19)
-> triggering divide by zero exception
-> handle and return
Then it will execute:
100 / inf -> Store 0 to c (no exception)
To confirm the looping behavior and the fix I used the following:
float fpu_div(float a, float b) {
float c;
asm volatile("lf.div.s %0, %1, %2"
: "+r" (c)
: "r" (a), "r" (b));
return c;
}
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/*
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* OpenRISC interrupt.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "gdbstub/helpers.h"
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#include "qemu/host-utils.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/loader.h"
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#endif
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void openrisc_cpu_do_interrupt(CPUState *cs)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUOpenRISCState *env = &cpu->env;
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int exception = cs->exception_index;
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env->epcr = env->pc;
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/* When we have an illegal instruction the error effective address
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shall be set to the illegal instruction address. */
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if (exception == EXCP_ILLEGAL) {
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env->eear = env->pc;
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}
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/* During exceptions esr is populared with the pre-exception sr. */
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env->esr = cpu_get_sr(env);
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/* In parallel sr is updated to disable mmu, interrupts, timers and
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set the delay slot exception flag. */
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env->sr &= ~SR_DME;
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env->sr &= ~SR_IME;
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env->sr |= SR_SM;
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env->sr &= ~SR_IEE;
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env->sr &= ~SR_TEE;
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env->pmr &= ~PMR_DME;
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env->pmr &= ~PMR_SME;
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env->lock_addr = -1;
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/* Set/clear dsx to indicate if we are in a delay slot exception. */
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if (env->dflag) {
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env->dflag = 0;
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env->sr |= SR_DSX;
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env->epcr -= 4;
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} else {
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env->sr &= ~SR_DSX;
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if (exception == EXCP_SYSCALL || exception == EXCP_FPE) {
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env->epcr += 4;
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}
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}
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if (exception > 0 && exception < EXCP_NR) {
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static const char * const int_name[EXCP_NR] = {
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[EXCP_RESET] = "RESET",
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[EXCP_BUSERR] = "BUSERR (bus error)",
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[EXCP_DPF] = "DFP (data protection fault)",
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[EXCP_IPF] = "IPF (code protection fault)",
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[EXCP_TICK] = "TICK (timer interrupt)",
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[EXCP_ALIGN] = "ALIGN",
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[EXCP_ILLEGAL] = "ILLEGAL",
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[EXCP_INT] = "INT (device interrupt)",
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[EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)",
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[EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)",
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[EXCP_RANGE] = "RANGE",
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[EXCP_SYSCALL] = "SYSCALL",
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[EXCP_FPE] = "FPE",
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[EXCP_TRAP] = "TRAP",
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};
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qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
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cs->cpu_index,
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int_name[exception]);
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hwaddr vect_pc = exception << 8;
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if (env->cpucfgr & CPUCFGR_EVBARP) {
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vect_pc |= env->evbar;
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}
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if (env->sr & SR_EPH) {
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vect_pc |= 0xf0000000;
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}
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env->pc = vect_pc;
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} else {
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cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
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}
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cs->exception_index = -1;
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}
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bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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CPUOpenRISCState *env = &cpu->env;
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int idx = -1;
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if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) {
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idx = EXCP_INT;
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}
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if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) {
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idx = EXCP_TICK;
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}
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if (idx >= 0) {
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cs->exception_index = idx;
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openrisc_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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