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4f67d30b5e
The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter. spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir . @@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
183 lines
5.0 KiB
C
183 lines
5.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Authors: Stafford Horne <shorne@gmail.com>
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "exec/memory.h"
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#define TYPE_OR1K_OMPIC "or1k-ompic"
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#define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC)
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#define OMPIC_CTRL_IRQ_ACK (1 << 31)
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#define OMPIC_CTRL_IRQ_GEN (1 << 30)
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#define OMPIC_CTRL_DST(cpu) (((cpu) >> 16) & 0x3fff)
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#define OMPIC_REG(addr) (((addr) >> 2) & 0x1)
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#define OMPIC_SRC_CPU(addr) (((addr) >> 3) & 0x4f)
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#define OMPIC_DST_CPU(addr) (((addr) >> 3) & 0x4f)
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#define OMPIC_STATUS_IRQ_PENDING (1 << 30)
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#define OMPIC_STATUS_SRC(cpu) (((cpu) & 0x3fff) << 16)
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#define OMPIC_STATUS_DATA(data) ((data) & 0xffff)
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#define OMPIC_CONTROL 0
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#define OMPIC_STATUS 1
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#define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */
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#define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */
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typedef struct OR1KOMPICState OR1KOMPICState;
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typedef struct OR1KOMPICCPUState OR1KOMPICCPUState;
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struct OR1KOMPICCPUState {
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qemu_irq irq;
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uint32_t status;
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uint32_t control;
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};
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struct OR1KOMPICState {
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SysBusDevice parent_obj;
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MemoryRegion mr;
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OR1KOMPICCPUState cpus[OMPIC_MAX_CPUS];
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uint32_t num_cpus;
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};
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static uint64_t ompic_read(void *opaque, hwaddr addr, unsigned size)
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{
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OR1KOMPICState *s = opaque;
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int src_cpu = OMPIC_SRC_CPU(addr);
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/* We can only write to control control, write control + update status */
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if (OMPIC_REG(addr) == OMPIC_CONTROL) {
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return s->cpus[src_cpu].control;
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} else {
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return s->cpus[src_cpu].status;
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}
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}
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static void ompic_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
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{
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OR1KOMPICState *s = opaque;
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/* We can only write to control control, write control + update status */
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if (OMPIC_REG(addr) == OMPIC_CONTROL) {
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int src_cpu = OMPIC_SRC_CPU(addr);
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s->cpus[src_cpu].control = data;
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if (data & OMPIC_CTRL_IRQ_GEN) {
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int dst_cpu = OMPIC_CTRL_DST(data);
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s->cpus[dst_cpu].status = OMPIC_STATUS_IRQ_PENDING |
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OMPIC_STATUS_SRC(src_cpu) |
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OMPIC_STATUS_DATA(data);
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qemu_irq_raise(s->cpus[dst_cpu].irq);
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}
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if (data & OMPIC_CTRL_IRQ_ACK) {
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s->cpus[src_cpu].status &= ~OMPIC_STATUS_IRQ_PENDING;
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qemu_irq_lower(s->cpus[src_cpu].irq);
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}
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}
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}
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static const MemoryRegionOps ompic_ops = {
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.read = ompic_read,
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.write = ompic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.max_access_size = 8,
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},
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};
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static void or1k_ompic_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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OR1KOMPICState *s = OR1K_OMPIC(obj);
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memory_region_init_io(&s->mr, OBJECT(s), &ompic_ops, s,
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"or1k-ompic", OMPIC_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->mr);
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}
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static void or1k_ompic_realize(DeviceState *dev, Error **errp)
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{
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OR1KOMPICState *s = OR1K_OMPIC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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int i;
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if (s->num_cpus > OMPIC_MAX_CPUS) {
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error_setg(errp, "Exceeded maximum CPUs %d", s->num_cpus);
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return;
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}
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/* Init IRQ sources for all CPUs */
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for (i = 0; i < s->num_cpus; i++) {
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sysbus_init_irq(sbd, &s->cpus[i].irq);
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}
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}
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static Property or1k_ompic_properties[] = {
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DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_or1k_ompic_cpu = {
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.name = "or1k_ompic_cpu",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(status, OR1KOMPICCPUState),
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VMSTATE_UINT32(control, OR1KOMPICCPUState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_or1k_ompic = {
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.name = TYPE_OR1K_OMPIC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_ARRAY(cpus, OR1KOMPICState, OMPIC_MAX_CPUS, 1,
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vmstate_or1k_ompic_cpu, OR1KOMPICCPUState),
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VMSTATE_UINT32(num_cpus, OR1KOMPICState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void or1k_ompic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, or1k_ompic_properties);
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dc->realize = or1k_ompic_realize;
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dc->vmsd = &vmstate_or1k_ompic;
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}
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static const TypeInfo or1k_ompic_info = {
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.name = TYPE_OR1K_OMPIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(OR1KOMPICState),
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.instance_init = or1k_ompic_init,
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.class_init = or1k_ompic_class_init,
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};
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static void or1k_ompic_register_types(void)
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{
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type_register_static(&or1k_ompic_info);
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}
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type_init(or1k_ompic_register_types)
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