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650d103d3e
In my "build everything" tree, changing hw/hw.h triggers a recompile of some 2600 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). The previous commits have left only the declaration of hw_error() in hw/hw.h. This permits dropping most of its inclusions. Touching it now recompiles less than 200 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20190812052359.30071-19-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
196 lines
4.7 KiB
C
196 lines
4.7 KiB
C
/*
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* LatticeMico32 CPU interrupt controller logic.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "migration/vmstate.h"
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#include "monitor/monitor.h"
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#include "qemu/module.h"
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#include "hw/sysbus.h"
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#include "trace.h"
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#include "hw/lm32/lm32_pic.h"
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#include "hw/intc/intc.h"
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#include "hw/irq.h"
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#define TYPE_LM32_PIC "lm32-pic"
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#define LM32_PIC(obj) OBJECT_CHECK(LM32PicState, (obj), TYPE_LM32_PIC)
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struct LM32PicState {
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SysBusDevice parent_obj;
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qemu_irq parent_irq;
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uint32_t im; /* interrupt mask */
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uint32_t ip; /* interrupt pending */
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uint32_t irq_state;
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/* statistics */
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uint64_t stats_irq_count[32];
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};
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typedef struct LM32PicState LM32PicState;
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static void update_irq(LM32PicState *s)
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{
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s->ip |= s->irq_state;
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if (s->ip & s->im) {
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trace_lm32_pic_raise_irq();
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qemu_irq_raise(s->parent_irq);
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} else {
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trace_lm32_pic_lower_irq();
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qemu_irq_lower(s->parent_irq);
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}
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}
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static void irq_handler(void *opaque, int irq, int level)
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{
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LM32PicState *s = opaque;
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assert(irq < 32);
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trace_lm32_pic_interrupt(irq, level);
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if (level) {
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s->irq_state |= (1 << irq);
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s->stats_irq_count[irq]++;
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} else {
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s->irq_state &= ~(1 << irq);
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}
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update_irq(s);
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}
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void lm32_pic_set_im(DeviceState *d, uint32_t im)
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{
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LM32PicState *s = LM32_PIC(d);
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trace_lm32_pic_set_im(im);
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s->im = im;
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update_irq(s);
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}
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void lm32_pic_set_ip(DeviceState *d, uint32_t ip)
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{
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LM32PicState *s = LM32_PIC(d);
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trace_lm32_pic_set_ip(ip);
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/* ack interrupt */
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s->ip &= ~ip;
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update_irq(s);
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}
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uint32_t lm32_pic_get_im(DeviceState *d)
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{
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LM32PicState *s = LM32_PIC(d);
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trace_lm32_pic_get_im(s->im);
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return s->im;
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}
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uint32_t lm32_pic_get_ip(DeviceState *d)
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{
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LM32PicState *s = LM32_PIC(d);
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trace_lm32_pic_get_ip(s->ip);
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return s->ip;
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}
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static void pic_reset(DeviceState *d)
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{
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LM32PicState *s = LM32_PIC(d);
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int i;
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s->im = 0;
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s->ip = 0;
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s->irq_state = 0;
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for (i = 0; i < 32; i++) {
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s->stats_irq_count[i] = 0;
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}
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}
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static bool lm32_get_statistics(InterruptStatsProvider *obj,
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uint64_t **irq_counts, unsigned int *nb_irqs)
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{
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LM32PicState *s = LM32_PIC(obj);
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*irq_counts = s->stats_irq_count;
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*nb_irqs = ARRAY_SIZE(s->stats_irq_count);
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return true;
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}
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static void lm32_print_info(InterruptStatsProvider *obj, Monitor *mon)
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{
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LM32PicState *s = LM32_PIC(obj);
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monitor_printf(mon, "lm32-pic: im=%08x ip=%08x irq_state=%08x\n",
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s->im, s->ip, s->irq_state);
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}
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static void lm32_pic_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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LM32PicState *s = LM32_PIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_in(dev, irq_handler, 32);
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sysbus_init_irq(sbd, &s->parent_irq);
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}
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static const VMStateDescription vmstate_lm32_pic = {
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.name = "lm32-pic",
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(im, LM32PicState),
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VMSTATE_UINT32(ip, LM32PicState),
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VMSTATE_UINT32(irq_state, LM32PicState),
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VMSTATE_UINT64_ARRAY(stats_irq_count, LM32PicState, 32),
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VMSTATE_END_OF_LIST()
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}
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};
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static void lm32_pic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
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dc->reset = pic_reset;
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dc->vmsd = &vmstate_lm32_pic;
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ic->get_statistics = lm32_get_statistics;
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ic->print_info = lm32_print_info;
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}
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static const TypeInfo lm32_pic_info = {
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.name = TYPE_LM32_PIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LM32PicState),
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.instance_init = lm32_pic_init,
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.class_init = lm32_pic_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_INTERRUPT_STATS_PROVIDER },
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{ }
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},
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};
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static void lm32_pic_register_types(void)
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{
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type_register_static(&lm32_pic_info);
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}
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type_init(lm32_pic_register_types)
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