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c82d9d43ed
This is majorly only for X86 because that's the only one that supports split irqchip for now. When the irqchip is split, we face a dilemma that KVM irqfd will be enabled, however the slow irqchip is still running in the userspace. It means that the resamplefd in the kernel irqfds won't take any effect and it will miss to ack INTx interrupts on EOIs. One example is split irqchip with VFIO INTx, which will break if we use the VFIO INTx fast path. This patch can potentially supports the VFIO fast path again for INTx, that the IRQ delivery will still use the fast path, while we don't need to trap MMIOs in QEMU for the device to emulate the EIOs (see the callers of vfio_eoi() hook). However the EOI of the INTx will still need to be done from the userspace by caching all the resamplefds in QEMU and kick properly for IOAPIC EOI broadcast. This is tricky because in this case the userspace ioapic irr & remote-irr will be bypassed. However such a change will greatly boost performance for assigned devices using INTx irqs (TCP_RR boosts 46% after this patch applied). When the userspace is responsible for the resamplefd kickup, don't register it on the kvm_irqfd anymore, because on newer kernels (after commit 654f1f13ea56, 5.2+) the KVM_IRQFD will fail if with both split irqchip and resamplefd. This will make sure that the fast path will work for all supported kernels. https://patchwork.kernel.org/patch/10738541/#22609933 Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Xu <peterx@redhat.com> Message-Id: <20200318145204.74483-5-peterx@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
515 lines
16 KiB
C
515 lines
16 KiB
C
/*
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* ioapic.c IOAPIC emulation logic
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* Split the ioapic logic from apic.c
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "monitor/monitor.h"
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#include "hw/i386/apic.h"
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#include "hw/i386/ioapic.h"
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#include "hw/i386/ioapic_internal.h"
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#include "hw/i386/x86.h"
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#include "hw/intc/i8259.h"
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#include "hw/pci/msi.h"
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#include "hw/qdev-properties.h"
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#include "sysemu/kvm.h"
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#include "sysemu/sysemu.h"
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#include "hw/i386/apic-msidef.h"
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#include "hw/i386/x86-iommu.h"
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#include "trace.h"
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#define APIC_DELIVERY_MODE_SHIFT 8
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#define APIC_POLARITY_SHIFT 14
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#define APIC_TRIG_MODE_SHIFT 15
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static IOAPICCommonState *ioapics[MAX_IOAPICS];
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/* global variable from ioapic_common.c */
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extern int ioapic_no;
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struct ioapic_entry_info {
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/* fields parsed from IOAPIC entries */
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uint8_t masked;
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uint8_t trig_mode;
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uint16_t dest_idx;
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uint8_t dest_mode;
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uint8_t delivery_mode;
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uint8_t vector;
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/* MSI message generated from above parsed fields */
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uint32_t addr;
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uint32_t data;
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};
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static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
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{
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memset(info, 0, sizeof(*info));
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info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
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info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
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/*
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* By default, this would be dest_id[8] + reserved[8]. When IR
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* is enabled, this would be interrupt_index[15] +
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* interrupt_format[1]. This field never means anything, but
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* only used to generate corresponding MSI.
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*/
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info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
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info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
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info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
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& IOAPIC_DM_MASK;
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if (info->delivery_mode == IOAPIC_DM_EXTINT) {
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info->vector = pic_read_irq(isa_pic);
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} else {
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info->vector = entry & IOAPIC_VECTOR_MASK;
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}
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info->addr = APIC_DEFAULT_ADDRESS | \
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(info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
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(info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
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info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
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(info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
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(info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
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}
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static void ioapic_service(IOAPICCommonState *s)
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{
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AddressSpace *ioapic_as = X86_MACHINE(qdev_get_machine())->ioapic_as;
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struct ioapic_entry_info info;
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uint8_t i;
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uint32_t mask;
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uint64_t entry;
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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mask = 1 << i;
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if (s->irr & mask) {
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int coalesce = 0;
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entry = s->ioredtbl[i];
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ioapic_entry_parse(entry, &info);
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if (!info.masked) {
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if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
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s->irr &= ~mask;
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} else {
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coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
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trace_ioapic_set_remote_irr(i);
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s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
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}
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if (coalesce) {
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/* We are level triggered interrupts, and the
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* guest should be still working on previous one,
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* so skip it. */
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continue;
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}
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#ifdef CONFIG_KVM
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if (kvm_irqchip_is_split()) {
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if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
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kvm_set_irq(kvm_state, i, 1);
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kvm_set_irq(kvm_state, i, 0);
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} else {
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kvm_set_irq(kvm_state, i, 1);
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}
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continue;
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}
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#endif
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/* No matter whether IR is enabled, we translate
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* the IOAPIC message into a MSI one, and its
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* address space will decide whether we need a
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* translation. */
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stl_le_phys(ioapic_as, info.addr, info.data);
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}
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}
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}
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}
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#define SUCCESSIVE_IRQ_MAX_COUNT 10000
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static void delayed_ioapic_service_cb(void *opaque)
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{
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IOAPICCommonState *s = opaque;
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ioapic_service(s);
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}
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static void ioapic_set_irq(void *opaque, int vector, int level)
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{
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IOAPICCommonState *s = opaque;
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/* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
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* to GSI 2. GSI maps to ioapic 1-1. This is not
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* the cleanest way of doing it but it should work. */
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trace_ioapic_set_irq(vector, level);
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ioapic_stat_update_irq(s, vector, level);
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if (vector == 0) {
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vector = 2;
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}
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if (vector < IOAPIC_NUM_PINS) {
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uint32_t mask = 1 << vector;
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uint64_t entry = s->ioredtbl[vector];
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if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
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IOAPIC_TRIGGER_LEVEL) {
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/* level triggered */
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if (level) {
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s->irr |= mask;
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if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
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ioapic_service(s);
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}
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} else {
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s->irr &= ~mask;
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}
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} else {
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/* According to the 82093AA manual, we must ignore edge requests
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* if the input pin is masked. */
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if (level && !(entry & IOAPIC_LVT_MASKED)) {
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s->irr |= mask;
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ioapic_service(s);
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}
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}
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}
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}
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static void ioapic_update_kvm_routes(IOAPICCommonState *s)
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{
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#ifdef CONFIG_KVM
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int i;
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if (kvm_irqchip_is_split()) {
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for (i = 0; i < IOAPIC_NUM_PINS; i++) {
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MSIMessage msg;
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struct ioapic_entry_info info;
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ioapic_entry_parse(s->ioredtbl[i], &info);
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if (!info.masked) {
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msg.address = info.addr;
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msg.data = info.data;
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kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
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}
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}
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kvm_irqchip_commit_routes(kvm_state);
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}
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#endif
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}
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#ifdef CONFIG_KVM
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static void ioapic_iec_notifier(void *private, bool global,
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uint32_t index, uint32_t mask)
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{
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IOAPICCommonState *s = (IOAPICCommonState *)private;
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/* For simplicity, we just update all the routes */
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ioapic_update_kvm_routes(s);
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}
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#endif
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void ioapic_eoi_broadcast(int vector)
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{
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IOAPICCommonState *s;
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uint64_t entry;
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int i, n;
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trace_ioapic_eoi_broadcast(vector);
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for (i = 0; i < MAX_IOAPICS; i++) {
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s = ioapics[i];
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if (!s) {
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continue;
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}
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for (n = 0; n < IOAPIC_NUM_PINS; n++) {
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entry = s->ioredtbl[n];
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if ((entry & IOAPIC_VECTOR_MASK) != vector ||
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((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) != IOAPIC_TRIGGER_LEVEL) {
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continue;
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}
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#ifdef CONFIG_KVM
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/*
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* When IOAPIC is in the userspace while APIC is still in
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* the kernel (i.e., split irqchip), we have a trick to
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* kick the resamplefd logic for registered irqfds from
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* userspace to deactivate the IRQ. When that happens, it
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* means the irq bypassed userspace IOAPIC (so the irr and
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* remote-irr of the table entry should be bypassed too
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* even if interrupt come). Still kick the resamplefds if
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* they're bound to the IRQ, to make sure to EOI the
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* interrupt for the hardware correctly.
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*
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* Note: We still need to go through the irr & remote-irr
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* operations below because we don't know whether there're
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* emulated devices that are using/sharing the same IRQ.
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*/
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kvm_resample_fd_notify(n);
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#endif
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if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
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continue;
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}
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trace_ioapic_clear_remote_irr(n, vector);
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s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
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if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
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++s->irq_eoi[n];
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if (s->irq_eoi[n] >= SUCCESSIVE_IRQ_MAX_COUNT) {
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/*
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* Real hardware does not deliver the interrupt immediately
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* during eoi broadcast, and this lets a buggy guest make
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* slow progress even if it does not correctly handle a
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* level-triggered interrupt. Emulate this behavior if we
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* detect an interrupt storm.
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*/
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s->irq_eoi[n] = 0;
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timer_mod_anticipate(s->delayed_ioapic_service_timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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NANOSECONDS_PER_SECOND / 100);
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trace_ioapic_eoi_delayed_reassert(n);
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} else {
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ioapic_service(s);
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}
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} else {
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s->irq_eoi[n] = 0;
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}
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}
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}
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}
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static uint64_t
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ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
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{
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IOAPICCommonState *s = opaque;
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int index;
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uint32_t val = 0;
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addr &= 0xff;
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switch (addr) {
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case IOAPIC_IOREGSEL:
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val = s->ioregsel;
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break;
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case IOAPIC_IOWIN:
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if (size != 4) {
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break;
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}
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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case IOAPIC_REG_ARB:
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val = s->id << IOAPIC_ID_SHIFT;
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break;
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case IOAPIC_REG_VER:
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val = s->version |
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((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
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break;
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default:
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index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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if (s->ioregsel & 1) {
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val = s->ioredtbl[index] >> 32;
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} else {
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val = s->ioredtbl[index] & 0xffffffff;
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}
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}
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}
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break;
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}
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trace_ioapic_mem_read(addr, s->ioregsel, size, val);
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return val;
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}
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/*
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* This is to satisfy the hack in Linux kernel. One hack of it is to
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* simulate clearing the Remote IRR bit of IOAPIC entry using the
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* following:
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*
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* "For IO-APIC's with EOI register, we use that to do an explicit EOI.
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* Otherwise, we simulate the EOI message manually by changing the trigger
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* mode to edge and then back to level, with RTE being masked during
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* this."
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*
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* (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
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*
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* This is based on the assumption that, Remote IRR bit will be
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* cleared by IOAPIC hardware when configured as edge-triggered
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* interrupts.
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*
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* Without this, level-triggered interrupts in IR mode might fail to
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* work correctly.
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*/
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static inline void
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ioapic_fix_edge_remote_irr(uint64_t *entry)
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{
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if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
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/* Edge-triggered interrupts, make sure remote IRR is zero */
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*entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
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}
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}
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static void
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ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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IOAPICCommonState *s = opaque;
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int index;
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addr &= 0xff;
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trace_ioapic_mem_write(addr, s->ioregsel, size, val);
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switch (addr) {
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case IOAPIC_IOREGSEL:
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s->ioregsel = val;
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break;
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case IOAPIC_IOWIN:
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if (size != 4) {
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break;
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}
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switch (s->ioregsel) {
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case IOAPIC_REG_ID:
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s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
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break;
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case IOAPIC_REG_VER:
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case IOAPIC_REG_ARB:
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break;
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default:
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index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
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if (index >= 0 && index < IOAPIC_NUM_PINS) {
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uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
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if (s->ioregsel & 1) {
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s->ioredtbl[index] &= 0xffffffff;
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s->ioredtbl[index] |= (uint64_t)val << 32;
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} else {
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s->ioredtbl[index] &= ~0xffffffffULL;
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s->ioredtbl[index] |= val;
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}
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/* restore RO bits */
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s->ioredtbl[index] &= IOAPIC_RW_BITS;
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s->ioredtbl[index] |= ro_bits;
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s->irq_eoi[index] = 0;
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ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
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ioapic_service(s);
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}
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}
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break;
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case IOAPIC_EOI:
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/* Explicit EOI is only supported for IOAPIC version 0x20 */
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if (size != 4 || s->version != 0x20) {
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break;
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}
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ioapic_eoi_broadcast(val);
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break;
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}
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ioapic_update_kvm_routes(s);
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}
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static const MemoryRegionOps ioapic_io_ops = {
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.read = ioapic_mem_read,
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.write = ioapic_mem_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void ioapic_machine_done_notify(Notifier *notifier, void *data)
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{
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#ifdef CONFIG_KVM
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IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
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machine_done);
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if (kvm_irqchip_is_split()) {
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X86IOMMUState *iommu = x86_iommu_get_default();
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if (iommu) {
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/* Register this IOAPIC with IOMMU IEC notifier, so that
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* when there are IR invalidates, we can be notified to
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* update kernel IR cache. */
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x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
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}
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}
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#endif
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}
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#define IOAPIC_VER_DEF 0x20
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static void ioapic_realize(DeviceState *dev, Error **errp)
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{
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IOAPICCommonState *s = IOAPIC_COMMON(dev);
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if (s->version != 0x11 && s->version != 0x20) {
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error_setg(errp, "IOAPIC only supports version 0x11 or 0x20 "
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"(default: 0x%x).", IOAPIC_VER_DEF);
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return;
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}
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memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
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|
"ioapic", 0x1000);
|
|
|
|
s->delayed_ioapic_service_timer =
|
|
timer_new_ns(QEMU_CLOCK_VIRTUAL, delayed_ioapic_service_cb, s);
|
|
|
|
qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
|
|
|
|
ioapics[ioapic_no] = s;
|
|
s->machine_done.notify = ioapic_machine_done_notify;
|
|
qemu_add_machine_init_done_notifier(&s->machine_done);
|
|
}
|
|
|
|
static void ioapic_unrealize(DeviceState *dev)
|
|
{
|
|
IOAPICCommonState *s = IOAPIC_COMMON(dev);
|
|
|
|
timer_del(s->delayed_ioapic_service_timer);
|
|
timer_free(s->delayed_ioapic_service_timer);
|
|
}
|
|
|
|
static Property ioapic_properties[] = {
|
|
DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ioapic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
k->realize = ioapic_realize;
|
|
k->unrealize = ioapic_unrealize;
|
|
/*
|
|
* If APIC is in kernel, we need to update the kernel cache after
|
|
* migration, otherwise first 24 gsi routes will be invalid.
|
|
*/
|
|
k->post_load = ioapic_update_kvm_routes;
|
|
dc->reset = ioapic_reset_common;
|
|
device_class_set_props(dc, ioapic_properties);
|
|
}
|
|
|
|
static const TypeInfo ioapic_info = {
|
|
.name = TYPE_IOAPIC,
|
|
.parent = TYPE_IOAPIC_COMMON,
|
|
.instance_size = sizeof(IOAPICCommonState),
|
|
.class_init = ioapic_class_init,
|
|
};
|
|
|
|
static void ioapic_register_types(void)
|
|
{
|
|
type_register_static(&ioapic_info);
|
|
}
|
|
|
|
type_init(ioapic_register_types)
|