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f4f643882d
Instead of accessing cpu interrupt vector directly from PIC, send the vector value over the qemu_irq. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
172 lines
4.6 KiB
C
172 lines
4.6 KiB
C
/*
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* QEMU ETRAX Interrupt Controller.
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*
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* Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qemu/module.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#define D(x)
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#define R_RW_MASK 0
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#define R_R_VECT 1
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#define R_R_MASKED_VECT 2
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#define R_R_NMI 3
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#define R_R_GURU 4
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#define R_MAX 5
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#define TYPE_ETRAX_FS_PIC "etraxfs,pic"
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#define ETRAX_FS_PIC(obj) \
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OBJECT_CHECK(struct etrax_pic, (obj), TYPE_ETRAX_FS_PIC)
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struct etrax_pic
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{
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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qemu_irq parent_irq;
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qemu_irq parent_nmi;
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uint32_t regs[R_MAX];
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};
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static void pic_update(struct etrax_pic *fs)
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{
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uint32_t vector = 0;
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int i;
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fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
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/* The ETRAX interrupt controller signals interrupts to the core
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through an interrupt request wire and an irq vector bus. If
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multiple interrupts are simultaneously active it chooses vector
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0x30 and lets the sw choose the priorities. */
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if (fs->regs[R_R_MASKED_VECT]) {
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uint32_t mv = fs->regs[R_R_MASKED_VECT];
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for (i = 0; i < 31; i++) {
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if (mv & 1) {
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vector = 0x31 + i;
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/* Check for multiple interrupts. */
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if (mv > 1)
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vector = 0x30;
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break;
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}
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mv >>= 1;
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}
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}
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qemu_set_irq(fs->parent_irq, vector);
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}
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static uint64_t
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pic_read(void *opaque, hwaddr addr, unsigned int size)
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{
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struct etrax_pic *fs = opaque;
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uint32_t rval;
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rval = fs->regs[addr >> 2];
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D(printf("%s %x=%x\n", __func__, addr, rval));
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return rval;
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}
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static void pic_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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struct etrax_pic *fs = opaque;
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D(printf("%s addr=%x val=%x\n", __func__, addr, value));
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if (addr == R_RW_MASK) {
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fs->regs[R_RW_MASK] = value;
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pic_update(fs);
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}
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}
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static const MemoryRegionOps pic_ops = {
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.read = pic_read,
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.write = pic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static void nmi_handler(void *opaque, int irq, int level)
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{
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struct etrax_pic *fs = (void *)opaque;
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uint32_t mask;
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mask = 1 << irq;
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if (level)
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fs->regs[R_R_NMI] |= mask;
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else
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fs->regs[R_R_NMI] &= ~mask;
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qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);
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}
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static void irq_handler(void *opaque, int irq, int level)
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{
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struct etrax_pic *fs = (void *)opaque;
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if (irq >= 30) {
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nmi_handler(opaque, irq, level);
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return;
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}
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irq -= 1;
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fs->regs[R_R_VECT] &= ~(1 << irq);
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fs->regs[R_R_VECT] |= (!!level << irq);
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pic_update(fs);
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}
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static void etraxfs_pic_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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struct etrax_pic *s = ETRAX_FS_PIC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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qdev_init_gpio_in(dev, irq_handler, 32);
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sysbus_init_irq(sbd, &s->parent_irq);
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sysbus_init_irq(sbd, &s->parent_nmi);
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memory_region_init_io(&s->mmio, obj, &pic_ops, s,
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"etraxfs-pic", R_MAX * 4);
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sysbus_init_mmio(sbd, &s->mmio);
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}
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static const TypeInfo etraxfs_pic_info = {
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.name = TYPE_ETRAX_FS_PIC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(struct etrax_pic),
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.instance_init = etraxfs_pic_init,
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};
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static void etraxfs_pic_register_types(void)
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{
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type_register_static(&etraxfs_pic_info);
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}
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type_init(etraxfs_pic_register_types)
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