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b69c3c21a5
Devices may have component devices and buses. Device realization may fail. Realization is recursive: a device's realize() method realizes its components, and device_set_realized() realizes its buses (which should in turn realize the devices on that bus, except bus_set_realized() doesn't implement that, yet). When realization of a component or bus fails, we need to roll back: unrealize everything we realized so far. If any of these unrealizes failed, the device would be left in an inconsistent state. Must not happen. device_set_realized() lets it happen: it ignores errors in the roll back code starting at label child_realize_fail. Since realization is recursive, unrealization must be recursive, too. But how could a partly failed unrealize be rolled back? We'd have to re-realize, which can fail. This design is fundamentally broken. device_set_realized() does not roll back at all. Instead, it keeps unrealizing, ignoring further errors. It can screw up even for a device with no buses: if the lone dc->unrealize() fails, it still unregisters vmstate, and calls listeners' unrealize() callback. bus_set_realized() does not roll back either. Instead, it stops unrealizing. Fortunately, no unrealize method can fail, as we'll see below. To fix the design error, drop parameter @errp from all the unrealize methods. Any unrealize method that uses @errp now needs an update. This leads us to unrealize() methods that can fail. Merely passing it to another unrealize method cannot cause failure, though. Here are the ones that do other things with @errp: * virtio_serial_device_unrealize() Fails when qbus_set_hotplug_handler() fails, but still does all the other work. On failure, the device would stay realized with its resources completely gone. Oops. Can't happen, because qbus_set_hotplug_handler() can't actually fail here. Pass &error_abort to qbus_set_hotplug_handler() instead. * hw/ppc/spapr_drc.c's unrealize() Fails when object_property_del() fails, but all the other work is already done. On failure, the device would stay realized with its vmstate registration gone. Oops. Can't happen, because object_property_del() can't actually fail here. Pass &error_abort to object_property_del() instead. * spapr_phb_unrealize() Fails and bails out when remove_drcs() fails, but other work is already done. On failure, the device would stay realized with some of its resources gone. Oops. remove_drcs() fails only when chassis_from_bus()'s object_property_get_uint() fails, and it can't here. Pass &error_abort to remove_drcs() instead. Therefore, no unrealize method can fail before this patch. device_set_realized()'s recursive unrealization via bus uses object_property_set_bool(). Can't drop @errp there, so pass &error_abort. We similarly unrealize with object_property_set_bool() elsewhere, always ignoring errors. Pass &error_abort instead. Several unrealize methods no longer handle errors from other unrealize methods: virtio_9p_device_unrealize(), virtio_input_device_unrealize(), scsi_qdev_unrealize(), ... Much of the deleted error handling looks wrong anyway. One unrealize methods no longer ignore such errors: usb_ehci_pci_exit(). Several realize methods no longer ignore errors when rolling back: v9fs_device_realize_common(), pci_qdev_unrealize(), spapr_phb_realize(), usb_qdev_realize(), vfio_ccw_realize(), virtio_device_realize(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-17-armbru@redhat.com>
482 lines
13 KiB
C
482 lines
13 KiB
C
/*
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* APIC support - common bits of emulated and KVM kernel model
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qapi/visitor.h"
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#include "hw/i386/apic.h"
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#include "hw/i386/apic_internal.h"
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#include "trace.h"
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#include "sysemu/hax.h"
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#include "sysemu/kvm.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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static int apic_irq_delivered;
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bool apic_report_tpr_access;
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void cpu_set_apic_base(DeviceState *dev, uint64_t val)
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{
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trace_cpu_set_apic_base(val);
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if (dev) {
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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/* switching to x2APIC, reset possibly modified xAPIC ID */
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if (!(s->apicbase & MSR_IA32_APICBASE_EXTD) &&
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(val & MSR_IA32_APICBASE_EXTD)) {
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s->id = s->initial_apic_id;
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}
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info->set_base(s, val);
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}
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}
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uint64_t cpu_get_apic_base(DeviceState *dev)
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{
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if (dev) {
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APICCommonState *s = APIC_COMMON(dev);
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trace_cpu_get_apic_base((uint64_t)s->apicbase);
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return s->apicbase;
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} else {
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trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
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return MSR_IA32_APICBASE_BSP;
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}
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}
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void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
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{
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APICCommonState *s;
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APICCommonClass *info;
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if (!dev) {
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return;
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}
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s = APIC_COMMON(dev);
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info = APIC_COMMON_GET_CLASS(s);
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info->set_tpr(s, val);
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}
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uint8_t cpu_get_apic_tpr(DeviceState *dev)
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{
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APICCommonState *s;
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APICCommonClass *info;
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if (!dev) {
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return 0;
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}
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s = APIC_COMMON(dev);
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info = APIC_COMMON_GET_CLASS(s);
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return info->get_tpr(s);
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}
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void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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apic_report_tpr_access = enable;
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if (info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, enable);
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}
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}
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void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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s->vapic_paddr = paddr;
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info->vapic_base_update(s);
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}
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void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
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TPRAccess access)
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{
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APICCommonState *s = APIC_COMMON(dev);
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vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
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}
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void apic_report_irq_delivered(int delivered)
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{
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apic_irq_delivered += delivered;
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trace_apic_report_irq_delivered(apic_irq_delivered);
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}
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void apic_reset_irq_delivered(void)
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{
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/* Copy this into a local variable to encourage gcc to emit a plain
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* register for a sys/sdt.h marker. For details on this workaround, see:
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* https://sourceware.org/bugzilla/show_bug.cgi?id=13296
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*/
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volatile int a_i_d = apic_irq_delivered;
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trace_apic_reset_irq_delivered(a_i_d);
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apic_irq_delivered = 0;
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}
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int apic_get_irq_delivered(void)
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{
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trace_apic_get_irq_delivered(apic_irq_delivered);
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return apic_irq_delivered;
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}
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void apic_deliver_nmi(DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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info->external_nmi(s);
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}
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bool apic_next_timer(APICCommonState *s, int64_t current_time)
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{
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int64_t d;
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/* We need to store the timer state separately to support APIC
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* implementations that maintain a non-QEMU timer, e.g. inside the
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* host kernel. This open-coded state allows us to migrate between
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* both models. */
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s->timer_expiry = -1;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
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return false;
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}
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d = (current_time - s->initial_count_load_time) >> s->count_shift;
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if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
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if (!s->initial_count) {
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return false;
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}
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d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
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((uint64_t)s->initial_count + 1);
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} else {
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if (d >= s->initial_count) {
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return false;
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}
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d = (uint64_t)s->initial_count + 1;
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}
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s->next_time = s->initial_count_load_time + (d << s->count_shift);
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s->timer_expiry = s->next_time;
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return true;
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}
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void apic_init_reset(DeviceState *dev)
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{
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APICCommonState *s;
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APICCommonClass *info;
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int i;
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if (!dev) {
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return;
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}
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s = APIC_COMMON(dev);
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s->tpr = 0;
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s->spurious_vec = 0xff;
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s->log_dest = 0;
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s->dest_mode = 0xf;
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memset(s->isr, 0, sizeof(s->isr));
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memset(s->tmr, 0, sizeof(s->tmr));
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memset(s->irr, 0, sizeof(s->irr));
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for (i = 0; i < APIC_LVT_NB; i++) {
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s->lvt[i] = APIC_LVT_MASKED;
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}
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s->esr = 0;
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memset(s->icr, 0, sizeof(s->icr));
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s->divide_conf = 0;
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s->count_shift = 0;
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s->initial_count = 0;
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s->initial_count_load_time = 0;
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s->next_time = 0;
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s->wait_for_sipi = !cpu_is_bsp(s->cpu);
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if (s->timer) {
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timer_del(s->timer);
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}
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s->timer_expiry = -1;
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info = APIC_COMMON_GET_CLASS(s);
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if (info->reset) {
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info->reset(s);
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}
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}
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void apic_designate_bsp(DeviceState *dev, bool bsp)
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{
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if (dev == NULL) {
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return;
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}
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APICCommonState *s = APIC_COMMON(dev);
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if (bsp) {
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s->apicbase |= MSR_IA32_APICBASE_BSP;
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} else {
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s->apicbase &= ~MSR_IA32_APICBASE_BSP;
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}
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}
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static void apic_reset_common(DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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uint32_t bsp;
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bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
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s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
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s->id = s->initial_apic_id;
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apic_reset_irq_delivered();
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s->vapic_paddr = 0;
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info->vapic_base_update(s);
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apic_init_reset(dev);
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}
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static const VMStateDescription vmstate_apic_common;
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static void apic_common_realize(DeviceState *dev, Error **errp)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info;
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static DeviceState *vapic;
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uint32_t instance_id = s->initial_apic_id;
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/* Normally initial APIC ID should be no more than hundreds */
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assert(instance_id != VMSTATE_INSTANCE_ID_ANY);
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info = APIC_COMMON_GET_CLASS(s);
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info->realize(dev, errp);
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/* Note: We need at least 1M to map the VAPIC option ROM */
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if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
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!hax_enabled() && ram_size >= 1024 * 1024) {
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vapic = sysbus_create_simple("kvmvapic", -1, NULL);
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}
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s->vapic = vapic;
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if (apic_report_tpr_access && info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, true);
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}
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if (s->legacy_instance_id) {
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instance_id = VMSTATE_INSTANCE_ID_ANY;
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}
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vmstate_register_with_alias_id(NULL, instance_id, &vmstate_apic_common,
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s, -1, 0, NULL);
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}
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static void apic_common_unrealize(DeviceState *dev)
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{
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APICCommonState *s = APIC_COMMON(dev);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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vmstate_unregister(NULL, &vmstate_apic_common, s);
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info->unrealize(dev);
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if (apic_report_tpr_access && info->enable_tpr_reporting) {
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info->enable_tpr_reporting(s, false);
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}
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}
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static int apic_pre_load(void *opaque)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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/* The default is !cpu_is_bsp(s->cpu), but the common value is 0
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* so that's what apic_common_sipi_needed checks for. Reset to
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* the value that is assumed when the apic_sipi subsection is
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* absent.
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*/
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s->wait_for_sipi = 0;
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return 0;
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}
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static int apic_dispatch_pre_save(void *opaque)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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if (info->pre_save) {
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info->pre_save(s);
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}
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return 0;
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}
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static int apic_dispatch_post_load(void *opaque, int version_id)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
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if (info->post_load) {
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info->post_load(s);
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}
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return 0;
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}
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static bool apic_common_sipi_needed(void *opaque)
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{
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APICCommonState *s = APIC_COMMON(opaque);
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return s->wait_for_sipi != 0;
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}
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static const VMStateDescription vmstate_apic_common_sipi = {
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.name = "apic_sipi",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = apic_common_sipi_needed,
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.fields = (VMStateField[]) {
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VMSTATE_INT32(sipi_vector, APICCommonState),
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VMSTATE_INT32(wait_for_sipi, APICCommonState),
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VMSTATE_END_OF_LIST()
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}
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};
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static const VMStateDescription vmstate_apic_common = {
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.name = "apic",
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.version_id = 3,
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.minimum_version_id = 3,
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.pre_load = apic_pre_load,
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.pre_save = apic_dispatch_pre_save,
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.post_load = apic_dispatch_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(apicbase, APICCommonState),
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VMSTATE_UINT8(id, APICCommonState),
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VMSTATE_UINT8(arb_id, APICCommonState),
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VMSTATE_UINT8(tpr, APICCommonState),
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VMSTATE_UINT32(spurious_vec, APICCommonState),
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VMSTATE_UINT8(log_dest, APICCommonState),
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VMSTATE_UINT8(dest_mode, APICCommonState),
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VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
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VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
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VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
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VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
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VMSTATE_UINT32(esr, APICCommonState),
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VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
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VMSTATE_UINT32(divide_conf, APICCommonState),
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VMSTATE_INT32(count_shift, APICCommonState),
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VMSTATE_UINT32(initial_count, APICCommonState),
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VMSTATE_INT64(initial_count_load_time, APICCommonState),
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VMSTATE_INT64(next_time, APICCommonState),
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VMSTATE_INT64(timer_expiry,
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APICCommonState), /* open-coded timer state */
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VMSTATE_END_OF_LIST()
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},
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.subsections = (const VMStateDescription*[]) {
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&vmstate_apic_common_sipi,
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NULL
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}
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};
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static Property apic_properties_common[] = {
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DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
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DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
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true),
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DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id,
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false),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void apic_common_get_id(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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APICCommonState *s = APIC_COMMON(obj);
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uint32_t value;
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value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id;
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visit_type_uint32(v, name, &value, errp);
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}
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static void apic_common_set_id(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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APICCommonState *s = APIC_COMMON(obj);
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DeviceState *dev = DEVICE(obj);
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Error *local_err = NULL;
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uint32_t value;
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if (dev->realized) {
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qdev_prop_set_after_realize(dev, name, errp);
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return;
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}
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visit_type_uint32(v, name, &value, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
|
|
|
|
s->initial_apic_id = value;
|
|
s->id = (uint8_t)value;
|
|
}
|
|
|
|
static void apic_common_initfn(Object *obj)
|
|
{
|
|
APICCommonState *s = APIC_COMMON(obj);
|
|
|
|
s->id = s->initial_apic_id = -1;
|
|
object_property_add(obj, "id", "uint32",
|
|
apic_common_get_id,
|
|
apic_common_set_id, NULL, NULL);
|
|
}
|
|
|
|
static void apic_common_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->reset = apic_reset_common;
|
|
device_class_set_props(dc, apic_properties_common);
|
|
dc->realize = apic_common_realize;
|
|
dc->unrealize = apic_common_unrealize;
|
|
/*
|
|
* Reason: APIC and CPU need to be wired up by
|
|
* x86_cpu_apic_create()
|
|
*/
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo apic_common_type = {
|
|
.name = TYPE_APIC_COMMON,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(APICCommonState),
|
|
.instance_init = apic_common_initfn,
|
|
.class_size = sizeof(APICCommonClass),
|
|
.class_init = apic_common_class_init,
|
|
.abstract = true,
|
|
};
|
|
|
|
static void apic_common_register_types(void)
|
|
{
|
|
type_register_static(&apic_common_type);
|
|
}
|
|
|
|
type_init(apic_common_register_types)
|