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b69c3c21a5
Devices may have component devices and buses. Device realization may fail. Realization is recursive: a device's realize() method realizes its components, and device_set_realized() realizes its buses (which should in turn realize the devices on that bus, except bus_set_realized() doesn't implement that, yet). When realization of a component or bus fails, we need to roll back: unrealize everything we realized so far. If any of these unrealizes failed, the device would be left in an inconsistent state. Must not happen. device_set_realized() lets it happen: it ignores errors in the roll back code starting at label child_realize_fail. Since realization is recursive, unrealization must be recursive, too. But how could a partly failed unrealize be rolled back? We'd have to re-realize, which can fail. This design is fundamentally broken. device_set_realized() does not roll back at all. Instead, it keeps unrealizing, ignoring further errors. It can screw up even for a device with no buses: if the lone dc->unrealize() fails, it still unregisters vmstate, and calls listeners' unrealize() callback. bus_set_realized() does not roll back either. Instead, it stops unrealizing. Fortunately, no unrealize method can fail, as we'll see below. To fix the design error, drop parameter @errp from all the unrealize methods. Any unrealize method that uses @errp now needs an update. This leads us to unrealize() methods that can fail. Merely passing it to another unrealize method cannot cause failure, though. Here are the ones that do other things with @errp: * virtio_serial_device_unrealize() Fails when qbus_set_hotplug_handler() fails, but still does all the other work. On failure, the device would stay realized with its resources completely gone. Oops. Can't happen, because qbus_set_hotplug_handler() can't actually fail here. Pass &error_abort to qbus_set_hotplug_handler() instead. * hw/ppc/spapr_drc.c's unrealize() Fails when object_property_del() fails, but all the other work is already done. On failure, the device would stay realized with its vmstate registration gone. Oops. Can't happen, because object_property_del() can't actually fail here. Pass &error_abort to object_property_del() instead. * spapr_phb_unrealize() Fails and bails out when remove_drcs() fails, but other work is already done. On failure, the device would stay realized with some of its resources gone. Oops. remove_drcs() fails only when chassis_from_bus()'s object_property_get_uint() fails, and it can't here. Pass &error_abort to remove_drcs() instead. Therefore, no unrealize method can fail before this patch. device_set_realized()'s recursive unrealization via bus uses object_property_set_bool(). Can't drop @errp there, so pass &error_abort. We similarly unrealize with object_property_set_bool() elsewhere, always ignoring errors. Pass &error_abort instead. Several unrealize methods no longer handle errors from other unrealize methods: virtio_9p_device_unrealize(), virtio_input_device_unrealize(), scsi_qdev_unrealize(), ... Much of the deleted error handling looks wrong anyway. One unrealize methods no longer ignore such errors: usb_ehci_pci_exit(). Several realize methods no longer ignore errors when rolling back: v9fs_device_realize_common(), pci_qdev_unrealize(), spapr_phb_realize(), usb_qdev_realize(), vfio_ccw_realize(), virtio_device_realize(). Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20200505152926.18877-17-armbru@redhat.com>
941 lines
24 KiB
C
941 lines
24 KiB
C
/*
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* APIC support
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/thread.h"
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#include "hw/i386/apic_internal.h"
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#include "hw/i386/apic.h"
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#include "hw/i386/ioapic.h"
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#include "hw/intc/i8259.h"
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#include "hw/pci/msi.h"
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#include "qemu/host-utils.h"
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#include "trace.h"
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#include "hw/i386/apic-msidef.h"
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#include "qapi/error.h"
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#define MAX_APICS 255
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#define MAX_APIC_WORDS 8
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#define SYNC_FROM_VAPIC 0x1
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#define SYNC_TO_VAPIC 0x2
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#define SYNC_ISR_IRR_TO_VAPIC 0x4
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static APICCommonState *local_apics[MAX_APICS + 1];
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#define TYPE_APIC "apic"
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#define APIC(obj) \
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OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC)
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static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode);
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static void apic_update_irq(APICCommonState *s);
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static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
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uint8_t dest, uint8_t dest_mode);
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/* Find first bit starting from msb */
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static int apic_fls_bit(uint32_t value)
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{
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return 31 - clz32(value);
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}
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/* Find first bit starting from lsb */
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static int apic_ffs_bit(uint32_t value)
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{
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return ctz32(value);
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}
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static inline void apic_reset_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] &= ~mask;
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}
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/* return -1 if no bit is set */
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static int get_highest_priority_int(uint32_t *tab)
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{
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int i;
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for (i = 7; i >= 0; i--) {
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if (tab[i] != 0) {
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return i * 32 + apic_fls_bit(tab[i]);
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}
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}
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return -1;
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}
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static void apic_sync_vapic(APICCommonState *s, int sync_type)
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{
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VAPICState vapic_state;
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size_t length;
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off_t start;
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int vector;
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if (!s->vapic_paddr) {
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return;
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}
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if (sync_type & SYNC_FROM_VAPIC) {
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cpu_physical_memory_read(s->vapic_paddr, &vapic_state,
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sizeof(vapic_state));
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s->tpr = vapic_state.tpr;
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}
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if (sync_type & (SYNC_TO_VAPIC | SYNC_ISR_IRR_TO_VAPIC)) {
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start = offsetof(VAPICState, isr);
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length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
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if (sync_type & SYNC_TO_VAPIC) {
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assert(qemu_cpu_is_self(CPU(s->cpu)));
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vapic_state.tpr = s->tpr;
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vapic_state.enabled = 1;
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start = 0;
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length = sizeof(VAPICState);
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}
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vector = get_highest_priority_int(s->isr);
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if (vector < 0) {
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vector = 0;
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}
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vapic_state.isr = vector & 0xf0;
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vapic_state.zero = 0;
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vector = get_highest_priority_int(s->irr);
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if (vector < 0) {
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vector = 0;
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}
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vapic_state.irr = vector & 0xff;
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address_space_write_rom(&address_space_memory,
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s->vapic_paddr + start,
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MEMTXATTRS_UNSPECIFIED,
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((void *)&vapic_state) + start, length);
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}
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}
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static void apic_vapic_base_update(APICCommonState *s)
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{
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apic_sync_vapic(s, SYNC_TO_VAPIC);
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}
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static void apic_local_deliver(APICCommonState *s, int vector)
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{
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uint32_t lvt = s->lvt[vector];
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int trigger_mode;
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trace_apic_local_deliver(vector, (lvt >> 8) & 7);
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if (lvt & APIC_LVT_MASKED)
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return;
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switch ((lvt >> 8) & 7) {
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case APIC_DM_SMI:
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SMI);
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break;
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case APIC_DM_NMI:
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_NMI);
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break;
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case APIC_DM_EXTINT:
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cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);
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break;
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case APIC_DM_FIXED:
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trigger_mode = APIC_TRIGGER_EDGE;
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if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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(lvt & APIC_LVT_LEVEL_TRIGGER))
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trigger_mode = APIC_TRIGGER_LEVEL;
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apic_set_irq(s, lvt & 0xff, trigger_mode);
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}
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}
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void apic_deliver_pic_intr(DeviceState *dev, int level)
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{
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APICCommonState *s = APIC(dev);
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if (level) {
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apic_local_deliver(s, APIC_LVT_LINT0);
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} else {
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uint32_t lvt = s->lvt[APIC_LVT_LINT0];
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switch ((lvt >> 8) & 7) {
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case APIC_DM_FIXED:
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if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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break;
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apic_reset_bit(s->irr, lvt & 0xff);
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/* fall through */
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case APIC_DM_EXTINT:
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apic_update_irq(s);
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break;
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}
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}
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}
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static void apic_external_nmi(APICCommonState *s)
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{
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apic_local_deliver(s, APIC_LVT_LINT1);
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}
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#define foreach_apic(apic, deliver_bitmask, code) \
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{\
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int __i, __j;\
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for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
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uint32_t __mask = deliver_bitmask[__i];\
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if (__mask) {\
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for(__j = 0; __j < 32; __j++) {\
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if (__mask & (1U << __j)) {\
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apic = local_apics[__i * 32 + __j];\
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if (apic) {\
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code;\
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}\
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}\
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}\
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}\
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}\
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}
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static void apic_bus_deliver(const uint32_t *deliver_bitmask,
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uint8_t delivery_mode, uint8_t vector_num,
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uint8_t trigger_mode)
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{
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APICCommonState *apic_iter;
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switch (delivery_mode) {
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case APIC_DM_LOWPRI:
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/* XXX: search for focus processor, arbitration */
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{
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int i, d;
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d = -1;
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for(i = 0; i < MAX_APIC_WORDS; i++) {
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if (deliver_bitmask[i]) {
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d = i * 32 + apic_ffs_bit(deliver_bitmask[i]);
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break;
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}
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}
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if (d >= 0) {
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apic_iter = local_apics[d];
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if (apic_iter) {
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apic_set_irq(apic_iter, vector_num, trigger_mode);
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}
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}
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}
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return;
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case APIC_DM_FIXED:
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break;
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case APIC_DM_SMI:
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_SMI)
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);
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return;
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case APIC_DM_NMI:
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(CPU(apic_iter->cpu), CPU_INTERRUPT_NMI)
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);
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return;
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case APIC_DM_INIT:
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/* normal INIT IPI sent to processors */
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foreach_apic(apic_iter, deliver_bitmask,
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cpu_interrupt(CPU(apic_iter->cpu),
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CPU_INTERRUPT_INIT)
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);
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return;
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case APIC_DM_EXTINT:
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/* handled in I/O APIC code */
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break;
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default:
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return;
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}
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foreach_apic(apic_iter, deliver_bitmask,
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apic_set_irq(apic_iter, vector_num, trigger_mode) );
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}
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void apic_deliver_irq(uint8_t dest, uint8_t dest_mode, uint8_t delivery_mode,
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uint8_t vector_num, uint8_t trigger_mode)
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{
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uint32_t deliver_bitmask[MAX_APIC_WORDS];
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trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
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trigger_mode);
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apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
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apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
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}
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static void apic_set_base(APICCommonState *s, uint64_t val)
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{
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s->apicbase = (val & 0xfffff000) |
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(s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
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/* if disabled, cannot be enabled again */
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if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
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cpu_clear_apic_feature(&s->cpu->env);
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s->spurious_vec &= ~APIC_SV_ENABLE;
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}
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}
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static void apic_set_tpr(APICCommonState *s, uint8_t val)
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{
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/* Updates from cr8 are ignored while the VAPIC is active */
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if (!s->vapic_paddr) {
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s->tpr = val << 4;
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apic_update_irq(s);
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}
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}
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int apic_get_highest_priority_irr(DeviceState *dev)
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{
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APICCommonState *s;
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if (!dev) {
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/* no interrupts */
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return -1;
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}
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s = APIC_COMMON(dev);
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return get_highest_priority_int(s->irr);
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}
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static uint8_t apic_get_tpr(APICCommonState *s)
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{
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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return s->tpr >> 4;
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}
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int apic_get_ppr(APICCommonState *s)
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{
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int tpr, isrv, ppr;
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tpr = (s->tpr >> 4);
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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isrv = 0;
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isrv >>= 4;
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if (tpr >= isrv)
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ppr = s->tpr;
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else
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ppr = isrv << 4;
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return ppr;
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}
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static int apic_get_arb_pri(APICCommonState *s)
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{
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/* XXX: arbitration */
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return 0;
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}
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/*
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* <0 - low prio interrupt,
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* 0 - no interrupt,
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* >0 - interrupt number
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*/
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static int apic_irq_pending(APICCommonState *s)
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{
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int irrv, ppr;
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if (!(s->spurious_vec & APIC_SV_ENABLE)) {
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return 0;
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}
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irrv = get_highest_priority_int(s->irr);
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if (irrv < 0) {
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return 0;
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}
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ppr = apic_get_ppr(s);
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if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
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return -1;
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}
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return irrv;
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}
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/* signal the CPU if an irq is pending */
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static void apic_update_irq(APICCommonState *s)
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{
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CPUState *cpu;
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DeviceState *dev = (DeviceState *)s;
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cpu = CPU(s->cpu);
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if (!qemu_cpu_is_self(cpu)) {
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cpu_interrupt(cpu, CPU_INTERRUPT_POLL);
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} else if (apic_irq_pending(s) > 0) {
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cpu_interrupt(cpu, CPU_INTERRUPT_HARD);
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} else if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
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cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);
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}
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}
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void apic_poll_irq(DeviceState *dev)
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{
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APICCommonState *s = APIC(dev);
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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apic_update_irq(s);
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}
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static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
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{
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apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
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apic_set_bit(s->irr, vector_num);
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if (trigger_mode)
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apic_set_bit(s->tmr, vector_num);
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else
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apic_reset_bit(s->tmr, vector_num);
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if (s->vapic_paddr) {
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apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
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/*
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* The vcpu thread needs to see the new IRR before we pull its current
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* TPR value. That way, if we miss a lowering of the TRP, the guest
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* has the chance to notice the new IRR and poll for IRQs on its own.
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*/
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smp_wmb();
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apic_sync_vapic(s, SYNC_FROM_VAPIC);
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}
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apic_update_irq(s);
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}
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static void apic_eoi(APICCommonState *s)
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{
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int isrv;
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isrv = get_highest_priority_int(s->isr);
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if (isrv < 0)
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return;
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apic_reset_bit(s->isr, isrv);
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if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
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ioapic_eoi_broadcast(isrv);
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}
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apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
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apic_update_irq(s);
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}
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static int apic_find_dest(uint8_t dest)
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{
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APICCommonState *apic = local_apics[dest];
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int i;
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if (apic && apic->id == dest)
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return dest; /* shortcut in case apic->id == local_apics[dest]->id */
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for (i = 0; i < MAX_APICS; i++) {
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apic = local_apics[i];
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if (apic && apic->id == dest)
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return i;
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if (!apic)
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break;
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}
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return -1;
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}
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|
|
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
|
|
uint8_t dest, uint8_t dest_mode)
|
|
{
|
|
APICCommonState *apic_iter;
|
|
int i;
|
|
|
|
if (dest_mode == 0) {
|
|
if (dest == 0xff) {
|
|
memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
|
|
} else {
|
|
int idx = apic_find_dest(dest);
|
|
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
|
|
if (idx >= 0)
|
|
apic_set_bit(deliver_bitmask, idx);
|
|
}
|
|
} else {
|
|
/* XXX: cluster mode */
|
|
memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
|
|
for(i = 0; i < MAX_APICS; i++) {
|
|
apic_iter = local_apics[i];
|
|
if (apic_iter) {
|
|
if (apic_iter->dest_mode == 0xf) {
|
|
if (dest & apic_iter->log_dest)
|
|
apic_set_bit(deliver_bitmask, i);
|
|
} else if (apic_iter->dest_mode == 0x0) {
|
|
if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
|
|
(dest & apic_iter->log_dest & 0x0f)) {
|
|
apic_set_bit(deliver_bitmask, i);
|
|
}
|
|
}
|
|
} else {
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void apic_startup(APICCommonState *s, int vector_num)
|
|
{
|
|
s->sipi_vector = vector_num;
|
|
cpu_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
|
|
}
|
|
|
|
void apic_sipi(DeviceState *dev)
|
|
{
|
|
APICCommonState *s = APIC(dev);
|
|
|
|
cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);
|
|
|
|
if (!s->wait_for_sipi)
|
|
return;
|
|
cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector);
|
|
s->wait_for_sipi = 0;
|
|
}
|
|
|
|
static void apic_deliver(DeviceState *dev, uint8_t dest, uint8_t dest_mode,
|
|
uint8_t delivery_mode, uint8_t vector_num,
|
|
uint8_t trigger_mode)
|
|
{
|
|
APICCommonState *s = APIC(dev);
|
|
uint32_t deliver_bitmask[MAX_APIC_WORDS];
|
|
int dest_shorthand = (s->icr[0] >> 18) & 3;
|
|
APICCommonState *apic_iter;
|
|
|
|
switch (dest_shorthand) {
|
|
case 0:
|
|
apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
|
|
break;
|
|
case 1:
|
|
memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
|
|
apic_set_bit(deliver_bitmask, s->id);
|
|
break;
|
|
case 2:
|
|
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
|
|
break;
|
|
case 3:
|
|
memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
|
|
apic_reset_bit(deliver_bitmask, s->id);
|
|
break;
|
|
}
|
|
|
|
switch (delivery_mode) {
|
|
case APIC_DM_INIT:
|
|
{
|
|
int trig_mode = (s->icr[0] >> 15) & 1;
|
|
int level = (s->icr[0] >> 14) & 1;
|
|
if (level == 0 && trig_mode == 1) {
|
|
foreach_apic(apic_iter, deliver_bitmask,
|
|
apic_iter->arb_id = apic_iter->id );
|
|
return;
|
|
}
|
|
}
|
|
break;
|
|
|
|
case APIC_DM_SIPI:
|
|
foreach_apic(apic_iter, deliver_bitmask,
|
|
apic_startup(apic_iter, vector_num) );
|
|
return;
|
|
}
|
|
|
|
apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, trigger_mode);
|
|
}
|
|
|
|
static bool apic_check_pic(APICCommonState *s)
|
|
{
|
|
DeviceState *dev = (DeviceState *)s;
|
|
|
|
if (!apic_accept_pic_intr(dev) || !pic_get_output(isa_pic)) {
|
|
return false;
|
|
}
|
|
apic_deliver_pic_intr(dev, 1);
|
|
return true;
|
|
}
|
|
|
|
int apic_get_interrupt(DeviceState *dev)
|
|
{
|
|
APICCommonState *s = APIC(dev);
|
|
int intno;
|
|
|
|
/* if the APIC is installed or enabled, we let the 8259 handle the
|
|
IRQs */
|
|
if (!s)
|
|
return -1;
|
|
if (!(s->spurious_vec & APIC_SV_ENABLE))
|
|
return -1;
|
|
|
|
apic_sync_vapic(s, SYNC_FROM_VAPIC);
|
|
intno = apic_irq_pending(s);
|
|
|
|
/* if there is an interrupt from the 8259, let the caller handle
|
|
* that first since ExtINT interrupts ignore the priority.
|
|
*/
|
|
if (intno == 0 || apic_check_pic(s)) {
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
return -1;
|
|
} else if (intno < 0) {
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
return s->spurious_vec & 0xff;
|
|
}
|
|
apic_reset_bit(s->irr, intno);
|
|
apic_set_bit(s->isr, intno);
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
|
|
apic_update_irq(s);
|
|
|
|
return intno;
|
|
}
|
|
|
|
int apic_accept_pic_intr(DeviceState *dev)
|
|
{
|
|
APICCommonState *s = APIC(dev);
|
|
uint32_t lvt0;
|
|
|
|
if (!s)
|
|
return -1;
|
|
|
|
lvt0 = s->lvt[APIC_LVT_LINT0];
|
|
|
|
if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
|
|
(lvt0 & APIC_LVT_MASKED) == 0)
|
|
return isa_pic != NULL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static uint32_t apic_get_current_count(APICCommonState *s)
|
|
{
|
|
int64_t d;
|
|
uint32_t val;
|
|
d = (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->initial_count_load_time) >>
|
|
s->count_shift;
|
|
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
|
/* periodic */
|
|
val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
|
} else {
|
|
if (d >= s->initial_count)
|
|
val = 0;
|
|
else
|
|
val = s->initial_count - d;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
static void apic_timer_update(APICCommonState *s, int64_t current_time)
|
|
{
|
|
if (apic_next_timer(s, current_time)) {
|
|
timer_mod(s->timer, s->next_time);
|
|
} else {
|
|
timer_del(s->timer);
|
|
}
|
|
}
|
|
|
|
static void apic_timer(void *opaque)
|
|
{
|
|
APICCommonState *s = opaque;
|
|
|
|
apic_local_deliver(s, APIC_LVT_TIMER);
|
|
apic_timer_update(s, s->next_time);
|
|
}
|
|
|
|
static uint64_t apic_mem_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
DeviceState *dev;
|
|
APICCommonState *s;
|
|
uint32_t val;
|
|
int index;
|
|
|
|
if (size < 4) {
|
|
return 0;
|
|
}
|
|
|
|
dev = cpu_get_current_apic();
|
|
if (!dev) {
|
|
return 0;
|
|
}
|
|
s = APIC(dev);
|
|
|
|
index = (addr >> 4) & 0xff;
|
|
switch(index) {
|
|
case 0x02: /* id */
|
|
val = s->id << 24;
|
|
break;
|
|
case 0x03: /* version */
|
|
val = s->version | ((APIC_LVT_NB - 1) << 16);
|
|
break;
|
|
case 0x08:
|
|
apic_sync_vapic(s, SYNC_FROM_VAPIC);
|
|
if (apic_report_tpr_access) {
|
|
cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
|
|
}
|
|
val = s->tpr;
|
|
break;
|
|
case 0x09:
|
|
val = apic_get_arb_pri(s);
|
|
break;
|
|
case 0x0a:
|
|
/* ppr */
|
|
val = apic_get_ppr(s);
|
|
break;
|
|
case 0x0b:
|
|
val = 0;
|
|
break;
|
|
case 0x0d:
|
|
val = s->log_dest << 24;
|
|
break;
|
|
case 0x0e:
|
|
val = (s->dest_mode << 28) | 0xfffffff;
|
|
break;
|
|
case 0x0f:
|
|
val = s->spurious_vec;
|
|
break;
|
|
case 0x10 ... 0x17:
|
|
val = s->isr[index & 7];
|
|
break;
|
|
case 0x18 ... 0x1f:
|
|
val = s->tmr[index & 7];
|
|
break;
|
|
case 0x20 ... 0x27:
|
|
val = s->irr[index & 7];
|
|
break;
|
|
case 0x28:
|
|
val = s->esr;
|
|
break;
|
|
case 0x30:
|
|
case 0x31:
|
|
val = s->icr[index & 1];
|
|
break;
|
|
case 0x32 ... 0x37:
|
|
val = s->lvt[index - 0x32];
|
|
break;
|
|
case 0x38:
|
|
val = s->initial_count;
|
|
break;
|
|
case 0x39:
|
|
val = apic_get_current_count(s);
|
|
break;
|
|
case 0x3e:
|
|
val = s->divide_conf;
|
|
break;
|
|
default:
|
|
s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
|
|
val = 0;
|
|
break;
|
|
}
|
|
trace_apic_mem_readl(addr, val);
|
|
return val;
|
|
}
|
|
|
|
static void apic_send_msi(MSIMessage *msi)
|
|
{
|
|
uint64_t addr = msi->address;
|
|
uint32_t data = msi->data;
|
|
uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
|
|
uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
|
|
uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
|
|
uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
|
|
uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
|
|
/* XXX: Ignore redirection hint. */
|
|
apic_deliver_irq(dest, dest_mode, delivery, vector, trigger_mode);
|
|
}
|
|
|
|
static void apic_mem_write(void *opaque, hwaddr addr, uint64_t val,
|
|
unsigned size)
|
|
{
|
|
DeviceState *dev;
|
|
APICCommonState *s;
|
|
int index = (addr >> 4) & 0xff;
|
|
|
|
if (size < 4) {
|
|
return;
|
|
}
|
|
|
|
if (addr > 0xfff || !index) {
|
|
/* MSI and MMIO APIC are at the same memory location,
|
|
* but actually not on the global bus: MSI is on PCI bus
|
|
* APIC is connected directly to the CPU.
|
|
* Mapping them on the global bus happens to work because
|
|
* MSI registers are reserved in APIC MMIO and vice versa. */
|
|
MSIMessage msi = { .address = addr, .data = val };
|
|
apic_send_msi(&msi);
|
|
return;
|
|
}
|
|
|
|
dev = cpu_get_current_apic();
|
|
if (!dev) {
|
|
return;
|
|
}
|
|
s = APIC(dev);
|
|
|
|
trace_apic_mem_writel(addr, val);
|
|
|
|
switch(index) {
|
|
case 0x02:
|
|
s->id = (val >> 24);
|
|
break;
|
|
case 0x03:
|
|
break;
|
|
case 0x08:
|
|
if (apic_report_tpr_access) {
|
|
cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
|
|
}
|
|
s->tpr = val;
|
|
apic_sync_vapic(s, SYNC_TO_VAPIC);
|
|
apic_update_irq(s);
|
|
break;
|
|
case 0x09:
|
|
case 0x0a:
|
|
break;
|
|
case 0x0b: /* EOI */
|
|
apic_eoi(s);
|
|
break;
|
|
case 0x0d:
|
|
s->log_dest = val >> 24;
|
|
break;
|
|
case 0x0e:
|
|
s->dest_mode = val >> 28;
|
|
break;
|
|
case 0x0f:
|
|
s->spurious_vec = val & 0x1ff;
|
|
apic_update_irq(s);
|
|
break;
|
|
case 0x10 ... 0x17:
|
|
case 0x18 ... 0x1f:
|
|
case 0x20 ... 0x27:
|
|
case 0x28:
|
|
break;
|
|
case 0x30:
|
|
s->icr[0] = val;
|
|
apic_deliver(dev, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
|
|
(s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
|
|
(s->icr[0] >> 15) & 1);
|
|
break;
|
|
case 0x31:
|
|
s->icr[1] = val;
|
|
break;
|
|
case 0x32 ... 0x37:
|
|
{
|
|
int n = index - 0x32;
|
|
s->lvt[n] = val;
|
|
if (n == APIC_LVT_TIMER) {
|
|
apic_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
|
|
} else if (n == APIC_LVT_LINT0 && apic_check_pic(s)) {
|
|
apic_update_irq(s);
|
|
}
|
|
}
|
|
break;
|
|
case 0x38:
|
|
s->initial_count = val;
|
|
s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
|
apic_timer_update(s, s->initial_count_load_time);
|
|
break;
|
|
case 0x39:
|
|
break;
|
|
case 0x3e:
|
|
{
|
|
int v;
|
|
s->divide_conf = val & 0xb;
|
|
v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
|
|
s->count_shift = (v + 1) & 7;
|
|
}
|
|
break;
|
|
default:
|
|
s->esr |= APIC_ESR_ILLEGAL_ADDRESS;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void apic_pre_save(APICCommonState *s)
|
|
{
|
|
apic_sync_vapic(s, SYNC_FROM_VAPIC);
|
|
}
|
|
|
|
static void apic_post_load(APICCommonState *s)
|
|
{
|
|
if (s->timer_expiry != -1) {
|
|
timer_mod(s->timer, s->timer_expiry);
|
|
} else {
|
|
timer_del(s->timer);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps apic_io_ops = {
|
|
.read = apic_mem_read,
|
|
.write = apic_mem_write,
|
|
.impl.min_access_size = 1,
|
|
.impl.max_access_size = 4,
|
|
.valid.min_access_size = 1,
|
|
.valid.max_access_size = 4,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
};
|
|
|
|
static void apic_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
APICCommonState *s = APIC(dev);
|
|
|
|
if (s->id >= MAX_APICS) {
|
|
error_setg(errp, "%s initialization failed. APIC ID %d is invalid",
|
|
object_get_typename(OBJECT(dev)), s->id);
|
|
return;
|
|
}
|
|
|
|
memory_region_init_io(&s->io_memory, OBJECT(s), &apic_io_ops, s, "apic-msi",
|
|
APIC_SPACE_SIZE);
|
|
|
|
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, apic_timer, s);
|
|
local_apics[s->id] = s;
|
|
|
|
msi_nonbroken = true;
|
|
}
|
|
|
|
static void apic_unrealize(DeviceState *dev)
|
|
{
|
|
APICCommonState *s = APIC(dev);
|
|
|
|
timer_del(s->timer);
|
|
timer_free(s->timer);
|
|
local_apics[s->id] = NULL;
|
|
}
|
|
|
|
static void apic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
APICCommonClass *k = APIC_COMMON_CLASS(klass);
|
|
|
|
k->realize = apic_realize;
|
|
k->unrealize = apic_unrealize;
|
|
k->set_base = apic_set_base;
|
|
k->set_tpr = apic_set_tpr;
|
|
k->get_tpr = apic_get_tpr;
|
|
k->vapic_base_update = apic_vapic_base_update;
|
|
k->external_nmi = apic_external_nmi;
|
|
k->pre_save = apic_pre_save;
|
|
k->post_load = apic_post_load;
|
|
k->send_msi = apic_send_msi;
|
|
}
|
|
|
|
static const TypeInfo apic_info = {
|
|
.name = TYPE_APIC,
|
|
.instance_size = sizeof(APICCommonState),
|
|
.parent = TYPE_APIC_COMMON,
|
|
.class_init = apic_class_init,
|
|
};
|
|
|
|
static void apic_register_types(void)
|
|
{
|
|
type_register_static(&apic_info);
|
|
}
|
|
|
|
type_init(apic_register_types)
|