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03385dfdaa
Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
174 lines
4.5 KiB
C
174 lines
4.5 KiB
C
/*
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* QEMU UniCore32 CPU
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*
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* Copyright (c) 2010-2012 Guan Xuetao
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Contributions from 2012-04-01 on are considered under GPL version 2,
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* or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "qemu-common.h"
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#include "migration/vmstate.h"
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#include "exec/exec-all.h"
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#include "fpu/softfloat.h"
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static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(cs);
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cpu->env.regs[31] = value;
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}
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static bool uc32_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
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}
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static inline void set_feature(CPUUniCore32State *env, int feature)
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{
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env->features |= feature;
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}
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/* CPU models */
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static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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typename = g_strdup_printf(UNICORE32_CPU_TYPE_NAME("%s"), cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) ||
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object_class_is_abstract(oc))) {
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oc = NULL;
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}
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return oc;
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}
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static void unicore_ii_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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env->cp0.c0_cpuid = 0x4d000863;
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env->cp0.c0_cachetype = 0x0d152152;
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env->cp0.c1_sys = 0x2000;
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env->cp0.c2_base = 0x0;
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env->cp0.c3_faultstatus = 0x0;
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env->cp0.c4_faultaddr = 0x0;
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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set_feature(env, UC32_HWCAP_CMOV);
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set_feature(env, UC32_HWCAP_UCF64);
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}
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static void uc32_any_cpu_initfn(Object *obj)
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{
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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env->cp0.c0_cpuid = 0xffffffff;
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env->ucf64.xregs[UC32_UCF64_FPSCR] = 0;
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set_feature(env, UC32_HWCAP_CMOV);
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set_feature(env, UC32_HWCAP_UCF64);
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}
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static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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qemu_init_vcpu(cs);
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ucc->parent_realize(dev, errp);
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}
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static void uc32_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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UniCore32CPU *cpu = UNICORE32_CPU(obj);
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CPUUniCore32State *env = &cpu->env;
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cs->env_ptr = env;
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#ifdef CONFIG_USER_ONLY
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env->uncached_asr = ASR_MODE_USER;
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env->regs[31] = 0;
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#else
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env->uncached_asr = ASR_MODE_PRIV;
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env->regs[31] = 0x03000000;
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#endif
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tlb_flush(cs);
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}
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static const VMStateDescription vmstate_uc32_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static void uc32_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, uc32_cpu_realizefn,
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&ucc->parent_realize);
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cc->class_by_name = uc32_cpu_class_by_name;
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cc->has_work = uc32_cpu_has_work;
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cc->do_interrupt = uc32_cpu_do_interrupt;
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cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt;
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cc->dump_state = uc32_cpu_dump_state;
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cc->set_pc = uc32_cpu_set_pc;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault;
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#else
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cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
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#endif
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cc->tcg_initialize = uc32_translate_init;
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dc->vmsd = &vmstate_uc32_cpu;
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}
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#define DEFINE_UNICORE32_CPU_TYPE(cpu_model, initfn) \
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{ \
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.parent = TYPE_UNICORE32_CPU, \
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.instance_init = initfn, \
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.name = UNICORE32_CPU_TYPE_NAME(cpu_model), \
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}
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static const TypeInfo uc32_cpu_type_infos[] = {
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{
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.name = TYPE_UNICORE32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(UniCore32CPU),
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.instance_init = uc32_cpu_initfn,
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.abstract = true,
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.class_size = sizeof(UniCore32CPUClass),
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.class_init = uc32_cpu_class_init,
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},
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DEFINE_UNICORE32_CPU_TYPE("UniCore-II", unicore_ii_cpu_initfn),
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DEFINE_UNICORE32_CPU_TYPE("any", uc32_any_cpu_initfn),
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};
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DEFINE_TYPES(uc32_cpu_type_infos)
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