mirror of
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d2b3eaefb4
This change moves the code that connects the SoC UART's to serial_hd's
to the machine.
It makes each UART a proper child member of the SoC, and then allows the
machine to selectively initialize the chardev for each UART with a
serial_hd.
This should preserve backwards compatibility, but also allow multi-SoC
boards to completely change the wiring of serial devices from the
command line to specific SoC UART's.
This also removes the uart-default property from the SoC, since the SoC
doesn't need to know what UART is the "default" on the machine anymore.
I tested this using the images and commands from the previous
refactoring, and another test image for the ast1030:
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd
wget https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd
wget https://github.com/peterdelevoryas/OpenBIC/releases/download/oby35-cl-2022.13.01/Y35BCL.elf
Fuji uses UART1:
qemu-system-arm -machine fuji-bmc \
-drive file=fuji.mtd,format=raw,if=mtd \
-nographic
ast2600-evb uses uart-default=UART5:
qemu-system-arm -machine ast2600-evb \
-drive file=fuji.mtd,format=raw,if=mtd \
-serial null -serial mon:stdio -display none
Wedge100 uses UART3:
qemu-system-arm -machine palmetto-bmc \
-drive file=wedge100.mtd,format=raw,if=mtd \
-serial null -serial null -serial null \
-serial mon:stdio -display none
AST1030 EVB uses UART5:
qemu-system-arm -machine ast1030-evb \
-kernel Y35BCL.elf -nographic
Fixes: 6827ff20b2
("hw: aspeed: Init all UART's with serial devices")
Signed-off-by: Peter Delevoryas <peter@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220705191400.41632-4-peter@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
647 lines
24 KiB
C
647 lines
24 KiB
C
/*
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* ASPEED SoC 2600 family
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*
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* Copyright (c) 2016-2019, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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#define ASPEED_SOC_DPMCU_SIZE 0x00040000
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static const hwaddr aspeed_soc_ast2600_memmap[] = {
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[ASPEED_DEV_SRAM] = 0x10000000,
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[ASPEED_DEV_DPMCU] = 0x18000000,
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/* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */
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[ASPEED_DEV_IOMEM] = 0x1E600000,
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[ASPEED_DEV_PWM] = 0x1E610000,
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[ASPEED_DEV_FMC] = 0x1E620000,
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[ASPEED_DEV_SPI1] = 0x1E630000,
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[ASPEED_DEV_SPI2] = 0x1E631000,
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[ASPEED_DEV_EHCI1] = 0x1E6A1000,
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[ASPEED_DEV_EHCI2] = 0x1E6A3000,
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[ASPEED_DEV_MII1] = 0x1E650000,
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[ASPEED_DEV_MII2] = 0x1E650008,
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[ASPEED_DEV_MII3] = 0x1E650010,
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[ASPEED_DEV_MII4] = 0x1E650018,
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[ASPEED_DEV_ETH1] = 0x1E660000,
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[ASPEED_DEV_ETH3] = 0x1E670000,
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[ASPEED_DEV_ETH2] = 0x1E680000,
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[ASPEED_DEV_ETH4] = 0x1E690000,
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[ASPEED_DEV_VIC] = 0x1E6C0000,
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[ASPEED_DEV_HACE] = 0x1E6D0000,
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[ASPEED_DEV_SDMC] = 0x1E6E0000,
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[ASPEED_DEV_SCU] = 0x1E6E2000,
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[ASPEED_DEV_XDMA] = 0x1E6E7000,
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[ASPEED_DEV_ADC] = 0x1E6E9000,
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[ASPEED_DEV_DP] = 0x1E6EB000,
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[ASPEED_DEV_SBC] = 0x1E6F2000,
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[ASPEED_DEV_EMMC_BC] = 0x1E6f5000,
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[ASPEED_DEV_VIDEO] = 0x1E700000,
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[ASPEED_DEV_SDHCI] = 0x1E740000,
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[ASPEED_DEV_EMMC] = 0x1E750000,
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[ASPEED_DEV_GPIO] = 0x1E780000,
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[ASPEED_DEV_GPIO_1_8V] = 0x1E780800,
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[ASPEED_DEV_RTC] = 0x1E781000,
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[ASPEED_DEV_TIMER1] = 0x1E782000,
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[ASPEED_DEV_WDT] = 0x1E785000,
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[ASPEED_DEV_LPC] = 0x1E789000,
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[ASPEED_DEV_IBT] = 0x1E789140,
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[ASPEED_DEV_I2C] = 0x1E78A000,
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[ASPEED_DEV_PECI] = 0x1E78B000,
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[ASPEED_DEV_UART1] = 0x1E783000,
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[ASPEED_DEV_UART2] = 0x1E78D000,
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[ASPEED_DEV_UART3] = 0x1E78E000,
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[ASPEED_DEV_UART4] = 0x1E78F000,
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[ASPEED_DEV_UART5] = 0x1E784000,
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[ASPEED_DEV_UART6] = 0x1E790000,
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[ASPEED_DEV_UART7] = 0x1E790100,
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[ASPEED_DEV_UART8] = 0x1E790200,
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[ASPEED_DEV_UART9] = 0x1E790300,
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[ASPEED_DEV_UART10] = 0x1E790400,
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[ASPEED_DEV_UART11] = 0x1E790500,
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[ASPEED_DEV_UART12] = 0x1E790600,
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[ASPEED_DEV_UART13] = 0x1E790700,
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[ASPEED_DEV_VUART] = 0x1E787000,
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[ASPEED_DEV_I3C] = 0x1E7A0000,
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[ASPEED_DEV_SDRAM] = 0x80000000,
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};
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#define ASPEED_A7MPCORE_ADDR 0x40460000
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#define AST2600_MAX_IRQ 197
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/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
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static const int aspeed_soc_ast2600_irqmap[] = {
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[ASPEED_DEV_UART1] = 47,
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[ASPEED_DEV_UART2] = 48,
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[ASPEED_DEV_UART3] = 49,
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[ASPEED_DEV_UART4] = 50,
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[ASPEED_DEV_UART5] = 8,
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[ASPEED_DEV_UART6] = 57,
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[ASPEED_DEV_UART7] = 58,
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[ASPEED_DEV_UART8] = 59,
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[ASPEED_DEV_UART9] = 60,
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[ASPEED_DEV_UART10] = 61,
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[ASPEED_DEV_UART11] = 62,
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[ASPEED_DEV_UART12] = 63,
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[ASPEED_DEV_UART13] = 64,
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[ASPEED_DEV_VUART] = 8,
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[ASPEED_DEV_FMC] = 39,
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[ASPEED_DEV_SDMC] = 0,
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[ASPEED_DEV_SCU] = 12,
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[ASPEED_DEV_ADC] = 78,
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[ASPEED_DEV_XDMA] = 6,
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[ASPEED_DEV_SDHCI] = 43,
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[ASPEED_DEV_EHCI1] = 5,
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[ASPEED_DEV_EHCI2] = 9,
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[ASPEED_DEV_EMMC] = 15,
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[ASPEED_DEV_GPIO] = 40,
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[ASPEED_DEV_GPIO_1_8V] = 11,
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[ASPEED_DEV_RTC] = 13,
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[ASPEED_DEV_TIMER1] = 16,
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[ASPEED_DEV_TIMER2] = 17,
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[ASPEED_DEV_TIMER3] = 18,
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[ASPEED_DEV_TIMER4] = 19,
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[ASPEED_DEV_TIMER5] = 20,
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[ASPEED_DEV_TIMER6] = 21,
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[ASPEED_DEV_TIMER7] = 22,
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[ASPEED_DEV_TIMER8] = 23,
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[ASPEED_DEV_WDT] = 24,
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[ASPEED_DEV_PWM] = 44,
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[ASPEED_DEV_LPC] = 35,
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[ASPEED_DEV_IBT] = 143,
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[ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
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[ASPEED_DEV_PECI] = 38,
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[ASPEED_DEV_ETH1] = 2,
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[ASPEED_DEV_ETH2] = 3,
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[ASPEED_DEV_HACE] = 4,
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[ASPEED_DEV_ETH3] = 32,
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[ASPEED_DEV_ETH4] = 33,
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[ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
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[ASPEED_DEV_DP] = 62,
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[ASPEED_DEV_I3C] = 102, /* 102 -> 107 */
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};
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static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]);
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}
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static void aspeed_soc_ast2600_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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char socname[8];
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char typename[64];
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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for (i = 0; i < sc->num_cpus; i++) {
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object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
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}
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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object_initialize_child(obj, "scu", &s->scu, typename);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2");
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key");
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object_initialize_child(obj, "a7mpcore", &s->a7mpcore,
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TYPE_A15MPCORE_PRIV);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
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snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
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object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
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snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
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object_initialize_child(obj, "adc", &s->adc, typename);
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snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
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object_initialize_child(obj, "i2c", &s->i2c, typename);
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object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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object_initialize_child(obj, "fmc", &s->fmc, typename);
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
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}
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for (i = 0; i < sc->ehcis_num; i++) {
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object_initialize_child(obj, "ehci[*]", &s->ehci[i],
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TYPE_PLATFORM_EHCI);
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}
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snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
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object_initialize_child(obj, "sdmc", &s->sdmc, typename);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size");
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
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}
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for (i = 0; i < sc->macs_num; i++) {
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object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
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TYPE_FTGMAC100);
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object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII);
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}
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for (i = 0; i < sc->uarts_num; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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}
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snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
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object_initialize_child(obj, "xdma", &s->xdma, typename);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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object_initialize_child(obj, "gpio", &s->gpio, typename);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname);
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object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename);
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object_initialize_child(obj, "sd-controller", &s->sdhci,
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TYPE_ASPEED_SDHCI);
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object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
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/* Init sd card slot class here so that they're under the correct parent */
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for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
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object_initialize_child(obj, "sd-controller.sdhci[*]",
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&s->sdhci.slots[i], TYPE_SYSBUS_SDHCI);
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}
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object_initialize_child(obj, "emmc-controller", &s->emmc,
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TYPE_ASPEED_SDHCI);
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object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort);
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object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
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TYPE_SYSBUS_SDHCI);
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object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
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snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
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object_initialize_child(obj, "hace", &s->hace, typename);
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object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
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object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
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object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "emmc-boot-controller",
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&s->emmc_boot_controller,
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TYPE_UNIMPLEMENTED_DEVICE);
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}
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/*
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* ASPEED ast2600 has 0xf as cluster ID
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*
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* https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register
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*/
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static uint64_t aspeed_calc_affinity(int cpu)
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{
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return (0xf << ARM_AFF1_SHIFT) | cpu;
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}
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static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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Error *err = NULL;
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qemu_irq irq;
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g_autofree char *sram_name = NULL;
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/* IO space */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
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sc->memmap[ASPEED_DEV_IOMEM],
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ASPEED_SOC_IOMEM_SIZE);
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/* Video engine stub */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
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sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
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/* eMMC Boot Controller stub */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller),
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"aspeed.emmc-boot-controller",
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sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000);
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/* CPU */
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for (i = 0; i < sc->num_cpus; i++) {
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if (sc->num_cpus > 1) {
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object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
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ASPEED_A7MPCORE_ADDR, &error_abort);
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}
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object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
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aspeed_calc_affinity(i), &error_abort);
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object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
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&error_abort);
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object_property_set_link(OBJECT(&s->cpu[i]), "memory",
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OBJECT(s->memory), &error_abort);
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if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
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return;
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}
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}
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/* A7MPCORE */
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object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
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&error_abort);
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object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
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ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
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&error_abort);
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sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->a7mpcore), 0, ASPEED_A7MPCORE_ADDR);
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for (i = 0; i < sc->num_cpus; i++) {
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SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
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DeviceState *d = DEVICE(&s->cpu[i]);
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irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
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sysbus_connect_irq(sbd, i, irq);
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irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
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sysbus_connect_irq(sbd, i + sc->num_cpus, irq);
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irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
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sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq);
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irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
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sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq);
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}
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/* SRAM */
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sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
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memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SRAM], &s->sram);
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/* DPMCU */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu",
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sc->memmap[ASPEED_DEV_DPMCU],
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ASPEED_SOC_DPMCU_SIZE);
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|
|
|
/* SCU */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
|
|
|
|
/* RTC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
|
|
|
|
/* Timer */
|
|
object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
|
|
sc->memmap[ASPEED_DEV_TIMER1]);
|
|
for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
|
|
qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
|
|
}
|
|
|
|
/* ADC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
|
|
|
|
/* UART */
|
|
if (!aspeed_soc_uart_realize(s, errp)) {
|
|
return;
|
|
}
|
|
|
|
/* I2C */
|
|
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
|
|
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
|
|
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_DEV_I2C] + i);
|
|
/* The AST2600 I2C controller has one IRQ per bus. */
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
|
|
}
|
|
|
|
/* PECI */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
|
|
sc->memmap[ASPEED_DEV_PECI]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
|
|
|
|
/* FMC, The number of CS is set at the board level */
|
|
object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
|
|
ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
|
|
|
|
/* SPI */
|
|
for (i = 0; i < sc->spis_num; i++) {
|
|
object_property_set_link(OBJECT(&s->spi[i]), "dram",
|
|
OBJECT(s->dram_mr), &error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
|
|
sc->memmap[ASPEED_DEV_SPI1 + i]);
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
|
|
ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
|
|
}
|
|
|
|
/* EHCI */
|
|
for (i = 0; i < sc->ehcis_num; i++) {
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
|
|
sc->memmap[ASPEED_DEV_EHCI1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
|
|
}
|
|
|
|
/* SDMC - SDRAM Memory Controller */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
|
|
sc->memmap[ASPEED_DEV_SDMC]);
|
|
|
|
/* Watch dog */
|
|
for (i = 0; i < sc->wdts_num; i++) {
|
|
AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
|
|
|
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
|
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
|
|
}
|
|
|
|
/* RAM */
|
|
if (!aspeed_soc_dram_init(s, errp)) {
|
|
return;
|
|
}
|
|
|
|
/* Net */
|
|
for (i = 0; i < sc->macs_num; i++) {
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
sc->memmap[ASPEED_DEV_ETH1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
|
|
|
|
object_property_set_link(OBJECT(&s->mii[i]), "nic",
|
|
OBJECT(&s->ftgmac100[i]), &error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) {
|
|
return;
|
|
}
|
|
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0,
|
|
sc->memmap[ASPEED_DEV_MII1 + i]);
|
|
}
|
|
|
|
/* XDMA */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
|
|
sc->memmap[ASPEED_DEV_XDMA]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
|
|
|
|
/* GPIO */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
|
|
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
|
|
sc->memmap[ASPEED_DEV_GPIO_1_8V]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V));
|
|
|
|
/* SDHCI */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
sc->memmap[ASPEED_DEV_SDHCI]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
|
|
|
|
/* eMMC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0,
|
|
sc->memmap[ASPEED_DEV_EMMC]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
|
|
|
|
/* LPC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
|
|
|
|
/* Connect the LPC IRQ to the GIC. It is otherwise unused. */
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
|
|
|
|
/*
|
|
* On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
|
|
*
|
|
* LPC subdevice IRQ sources are offset from 1 because the LPC model caters
|
|
* to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
|
|
* shared across the subdevices, and the shared IRQ output to the VIC is at
|
|
* offset 0.
|
|
*/
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
|
|
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
|
|
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
|
|
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
|
|
qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
|
|
|
|
/* HACE */
|
|
object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
|
|
sc->memmap[ASPEED_DEV_HACE]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
|
|
|
|
/* I3C */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]);
|
|
for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) {
|
|
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore),
|
|
sc->irqmap[ASPEED_DEV_I3C] + i);
|
|
/* The AST2600 I3C controller has one IRQ per bus. */
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
|
|
}
|
|
|
|
/* Secure Boot Controller */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
|
|
}
|
|
|
|
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
dc->realize = aspeed_soc_ast2600_realize;
|
|
|
|
sc->name = "ast2600-a3";
|
|
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7");
|
|
sc->silicon_rev = AST2600_A3_SILICON_REV;
|
|
sc->sram_size = 0x16400;
|
|
sc->spis_num = 2;
|
|
sc->ehcis_num = 2;
|
|
sc->wdts_num = 4;
|
|
sc->macs_num = 4;
|
|
sc->uarts_num = 13;
|
|
sc->irqmap = aspeed_soc_ast2600_irqmap;
|
|
sc->memmap = aspeed_soc_ast2600_memmap;
|
|
sc->num_cpus = 2;
|
|
sc->get_irq = aspeed_soc_ast2600_get_irq;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast2600_type_info = {
|
|
.name = "ast2600-a3",
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.instance_init = aspeed_soc_ast2600_init,
|
|
.class_init = aspeed_soc_ast2600_class_init,
|
|
.class_size = sizeof(AspeedSoCClass),
|
|
};
|
|
|
|
static void aspeed_soc_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_soc_ast2600_type_info);
|
|
};
|
|
|
|
type_init(aspeed_soc_register_types)
|