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5457dc9e37
TARGET_NR_select can have three different implementations:
1- to always return -ENOSYS
microblaze, ppc, ppc64
-> TARGET_WANT_NI_OLD_SELECT
2- to take parameters from a structure pointed by arg1
(kernel sys_old_select)
i386, arm, m68k
-> TARGET_WANT_OLD_SYS_SELECT
3- to take parameters from arg[1-5]
(kernel sys_select)
x86_64, alpha, s390x,
cris, sparc, sparc64
Some (new) architectures don't define NR_select,
4- but only NR__newselect with sys_select:
mips, mips64, sh
5- don't define NR__newselect, and use pselect6 syscall:
aarch64, openrisc, tilegx, unicore32
Reported-by: Timothy Pearson <tpearson@raptorengineering.com>
Reported-by: Allan Wirth <awirth@akamai.com>
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Riku Voipio <riku.voipio@linaro.org>
45 lines
1.0 KiB
C
45 lines
1.0 KiB
C
#ifndef ARM_TARGET_SYSCALL_H
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#define ARM_TARGET_SYSCALL_H
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/* this struct defines the way the registers are stored on the
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stack during a system call. */
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/* uregs[0..15] are r0 to r15; uregs[16] is CPSR; uregs[17] is ORIG_r0 */
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struct target_pt_regs {
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abi_long uregs[18];
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};
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#define ARM_SYSCALL_BASE 0x900000
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#define ARM_THUMB_SYSCALL 0
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#define ARM_NR_BASE 0xf0000
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#define ARM_NR_breakpoint (ARM_NR_BASE + 1)
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#define ARM_NR_cacheflush (ARM_NR_BASE + 2)
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#define ARM_NR_set_tls (ARM_NR_BASE + 5)
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#define ARM_NR_semihosting 0x123456
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#define ARM_NR_thumb_semihosting 0xAB
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#if defined(TARGET_WORDS_BIGENDIAN)
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#define UNAME_MACHINE "armv5teb"
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#else
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#define UNAME_MACHINE "armv5tel"
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#endif
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#define UNAME_MINIMUM_RELEASE "2.6.32"
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#define TARGET_CLONE_BACKWARDS
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#define TARGET_MINSIGSTKSZ 2048
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#define TARGET_MLOCKALL_MCL_CURRENT 1
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#define TARGET_MLOCKALL_MCL_FUTURE 2
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#define TARGET_WANT_OLD_SYS_SELECT
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#define TARGET_FORCE_SHMLBA
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static inline abi_ulong target_shmlba(CPUARMState *env)
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{
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return 4 * 4096;
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}
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#endif /* ARM_TARGET_SYSCALL_H */
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