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118f2aadbc
This prevents illegal instruction on cpus that do not support xgetbv. Buglink: https://bugs.launchpad.net/qemu/+bug/1758819 Reviewed-by: Cameron Esfahani <dirty@apple.com> Signed-off-by: Hill Ma <maahiuzeon@gmail.com> Message-Id: <X/6OJ7qk0W6bHkHQ@Hills-Mac-Pro.local> Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
165 lines
5.9 KiB
C
165 lines
5.9 KiB
C
/*
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* i386 CPUID helper functions
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* cpuid
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "x86.h"
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#include "vmx.h"
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#include "sysemu/hvf.h"
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static bool xgetbv(uint32_t cpuid_ecx, uint32_t idx, uint64_t *xcr)
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{
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uint32_t xcrl, xcrh;
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if (cpuid_ecx & CPUID_EXT_OSXSAVE) {
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/*
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* The xgetbv instruction is not available to older versions of
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* the assembler, so we encode the instruction manually.
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*/
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asm(".byte 0x0f, 0x01, 0xd0" : "=a" (xcrl), "=d" (xcrh) : "c" (idx));
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*xcr = (((uint64_t)xcrh) << 32) | xcrl;
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return true;
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}
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return false;
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}
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uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,
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int reg)
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{
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uint64_t cap;
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uint32_t eax, ebx, ecx, edx;
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host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);
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switch (func) {
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case 0:
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eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;
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break;
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case 1:
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edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
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CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
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CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
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CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |
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CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS;
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ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
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CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |
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CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |
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CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE |
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CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;
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ecx |= CPUID_EXT_HYPERVISOR;
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break;
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case 6:
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eax = CPUID_6_EAX_ARAT;
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ebx = 0;
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ecx = 0;
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edx = 0;
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break;
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case 7:
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if (idx == 0) {
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ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |
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CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
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CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |
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CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |
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CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |
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CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |
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CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |
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CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |
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CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |
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CPUID_7_0_EBX_INVPCID;
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hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
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if (!(cap & CPU_BASED2_INVPCID)) {
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ebx &= ~CPUID_7_0_EBX_INVPCID;
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}
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ecx &= CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;
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edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;
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} else {
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ebx = 0;
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ecx = 0;
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edx = 0;
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}
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eax = 0;
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break;
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case 0xD:
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if (idx == 0) {
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uint64_t host_xcr0;
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if (xgetbv(ecx, 0, &host_xcr0)) {
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uint64_t supp_xcr0 = host_xcr0 & (XSTATE_FP_MASK |
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XSTATE_SSE_MASK | XSTATE_YMM_MASK |
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XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
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XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK |
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XSTATE_Hi16_ZMM_MASK);
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eax &= supp_xcr0;
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}
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} else if (idx == 1) {
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hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
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eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;
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if (!(cap & CPU_BASED2_XSAVES_XRSTORS)) {
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eax &= ~CPUID_XSAVE_XSAVES;
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}
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}
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break;
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case 0x80000001:
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/* LM only if HVF in 64-bit mode */
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edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
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CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
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CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
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CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |
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CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |
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CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;
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hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);
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if (!(cap & CPU_BASED2_RDTSCP)) {
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edx &= ~CPUID_EXT2_RDTSCP;
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}
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hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);
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if (!(cap & CPU_BASED_TSC_OFFSET)) {
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edx &= ~CPUID_EXT2_RDTSCP;
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}
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ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |
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CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |
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CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;
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break;
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default:
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return 0;
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}
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switch (reg) {
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case R_EAX:
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return eax;
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case R_EBX:
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return ebx;
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case R_ECX:
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return ecx;
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case R_EDX:
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return edx;
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default:
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return 0;
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}
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}
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