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a8170e5e97
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
150 lines
3.2 KiB
C
150 lines
3.2 KiB
C
/*
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* Power Management device simulation in PKUnity SoC
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "hw.h"
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#include "sysbus.h"
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#undef DEBUG_PUV3
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#include "puv3.h"
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t reg_PMCR;
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uint32_t reg_PCGR;
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uint32_t reg_PLL_SYS_CFG;
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uint32_t reg_PLL_DDR_CFG;
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uint32_t reg_PLL_VGA_CFG;
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uint32_t reg_DIVCFG;
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} PUV3PMState;
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static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PUV3PMState *s = opaque;
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uint32_t ret = 0;
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switch (offset) {
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case 0x14:
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ret = s->reg_PCGR;
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break;
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case 0x18:
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ret = s->reg_PLL_SYS_CFG;
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break;
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case 0x1c:
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ret = s->reg_PLL_DDR_CFG;
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break;
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case 0x20:
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ret = s->reg_PLL_VGA_CFG;
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break;
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case 0x24:
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ret = s->reg_DIVCFG;
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break;
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case 0x28: /* PLL SYS STATUS */
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ret = 0x00002401;
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break;
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case 0x2c: /* PLL DDR STATUS */
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ret = 0x00100c00;
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break;
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case 0x30: /* PLL VGA STATUS */
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ret = 0x00003801;
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break;
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case 0x34: /* DIV STATUS */
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ret = 0x22f52015;
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break;
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case 0x38: /* SW RESET */
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ret = 0x0;
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break;
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case 0x44: /* PLL DFC DONE */
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ret = 0x7;
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break;
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default:
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DPRINTF("Bad offset 0x%x\n", offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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return ret;
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}
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static void puv3_pm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PUV3PMState *s = opaque;
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switch (offset) {
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case 0x0:
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s->reg_PMCR = value;
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break;
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case 0x14:
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s->reg_PCGR = value;
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break;
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case 0x18:
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s->reg_PLL_SYS_CFG = value;
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break;
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case 0x1c:
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s->reg_PLL_DDR_CFG = value;
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break;
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case 0x20:
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s->reg_PLL_VGA_CFG = value;
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break;
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case 0x24:
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case 0x38:
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break;
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default:
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DPRINTF("Bad offset 0x%x\n", offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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}
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static const MemoryRegionOps puv3_pm_ops = {
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.read = puv3_pm_read,
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.write = puv3_pm_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int puv3_pm_init(SysBusDevice *dev)
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{
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PUV3PMState *s = FROM_SYSBUS(PUV3PMState, dev);
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s->reg_PCGR = 0x0;
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memory_region_init_io(&s->iomem, &puv3_pm_ops, s, "puv3_pm",
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PUV3_REGS_OFFSET);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static void puv3_pm_class_init(ObjectClass *klass, void *data)
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{
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SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
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sdc->init = puv3_pm_init;
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}
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static const TypeInfo puv3_pm_info = {
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.name = "puv3_pm",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PUV3PMState),
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.class_init = puv3_pm_class_init,
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};
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static void puv3_pm_register_type(void)
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{
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type_register_static(&puv3_pm_info);
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}
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type_init(puv3_pm_register_type)
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