qemu/target/openrisc
Stafford Horne 6b4bbd6aeb openrisc/cputimer: Perparation for Multicore
In order to support multicore system we move some of the previously
static state variables into the state of each core.

On the other hand in order to allow timers to be synced between each
code the ttcr (tick timer count register) is moved out of the core.
This is not as per real hardware spec which has a separate timer counter
per core, but it seems the most simple way to keep each clock in sync.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-10-21 06:35:47 +09:00
..
cpu.c openrisc/cputimer: Perparation for Multicore 2017-10-21 06:35:47 +09:00
cpu.h openrisc/cputimer: Perparation for Multicore 2017-10-21 06:35:47 +09:00
exception_helper.c target/openrisc: Optimize for r0 being zero 2017-02-14 08:15:00 +11:00
exception.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
exception.h Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
fpu_helper.c target/openrisc: Fix madd 2017-02-14 08:15:00 +11:00
gdbstub.c target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
helper.h target/openrisc: Fix madd 2017-02-14 08:15:00 +11:00
interrupt_helper.c target/openrisc: Tidy ppc/npc implementation 2017-02-14 08:15:00 +11:00
interrupt.c target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
machine.c openrisc/cputimer: Perparation for Multicore 2017-10-21 06:35:47 +09:00
Makefile.objs target/openrisc: Streamline arithmetic and OVE 2017-02-14 08:14:59 +11:00
mmu_helper.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
mmu.c target/openrisc: Fixes for memory debugging 2017-05-04 09:38:49 +09:00
sys_helper.c openrisc/cputimer: Perparation for Multicore 2017-10-21 06:35:47 +09:00
translate.c target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00