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ebedf0f9cd
Add a const qom link between the CPU and the IIC instead of passing the CPU link through a qom property. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 20170317210627.23532-1-marex@denx.de Cc: Alexander Graf <agraf@suse.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Igor Mammedov <imammedo@redhat.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* QEMU Altera Internal Interrupt Controller.
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "cpu.h"
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#define TYPE_ALTERA_IIC "altera,iic"
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#define ALTERA_IIC(obj) \
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OBJECT_CHECK(AlteraIIC, (obj), TYPE_ALTERA_IIC)
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typedef struct AlteraIIC {
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SysBusDevice parent_obj;
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void *cpu;
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qemu_irq parent_irq;
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} AlteraIIC;
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static void update_irq(AlteraIIC *pv)
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{
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CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;
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qemu_set_irq(pv->parent_irq,
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env->regs[CR_IPENDING] & env->regs[CR_IENABLE]);
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}
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static void irq_handler(void *opaque, int irq, int level)
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{
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AlteraIIC *pv = opaque;
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CPUNios2State *env = &((Nios2CPU *)(pv->cpu))->env;
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env->regs[CR_IPENDING] &= ~(1 << irq);
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env->regs[CR_IPENDING] |= !!level << irq;
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update_irq(pv);
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}
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static void altera_iic_init(Object *obj)
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{
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AlteraIIC *pv = ALTERA_IIC(obj);
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qdev_init_gpio_in(DEVICE(pv), irq_handler, 32);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &pv->parent_irq);
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}
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static void altera_iic_realize(DeviceState *dev, Error **errp)
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{
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struct AlteraIIC *pv = ALTERA_IIC(dev);
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Error *err = NULL;
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pv->cpu = object_property_get_link(OBJECT(dev), "cpu", &err);
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if (!pv->cpu) {
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error_setg(errp, "altera,iic: CPU link not found: %s",
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error_get_pretty(err));
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return;
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}
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}
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static void altera_iic_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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/* Reason: needs to be wired up, e.g. by nios2_10m50_ghrd_init() */
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dc->cannot_instantiate_with_device_add_yet = true;
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dc->realize = altera_iic_realize;
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}
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static TypeInfo altera_iic_info = {
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.name = "altera,iic",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AlteraIIC),
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.instance_init = altera_iic_init,
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.class_init = altera_iic_class_init,
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};
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static void altera_iic_register(void)
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{
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type_register_static(&altera_iic_info);
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}
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type_init(altera_iic_register)
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