Peter Maydell f45cb2f43f target-mips: Avoid shifting left into sign bit ... Add U suffix to various places where we shift a 1 left by 31, to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2014-03-27 19:22:49 +04:00
..
cpu-qom.h	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
cpu.c	cputlb: Change tlb_flush() argument to CPUState	2014-03-13 19:52:47 +01:00
cpu.h	target-mips: Avoid shifting left into sign bit	2014-03-27 19:22:49 +04:00
dsp_helper.c	target-mips: Use macro ARRAY_SIZE where possible	2013-12-09 16:44:04 +01:00
gdbstub.c	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
helper.c	target-mips: Avoid shifting left into sign bit	2014-03-27 19:22:49 +04:00
helper.h	target-mips: add user-mode FR switch support for MIPS32r5	2014-02-10 16:46:38 +01:00
lmi_helper.c	target-mips: Implement Loongson Multimedia Instructions	2012-09-19 21:40:48 +02:00
machine.c	cputlb: Change tlb_flush() argument to CPUState	2014-03-13 19:52:47 +01:00
Makefile.objs	cpu: Introduce CPUClass::gdb_{read,write}_register()	2013-07-27 00:04:17 +02:00
mips-defs.h	target-mips: add CPU definition for MIPS32R5	2014-02-10 16:45:53 +01:00
op_helper.c	target-mips: Avoid shifting left into sign bit	2014-03-27 19:22:49 +04:00
TODO	target-mips: Change TODO file	2012-10-31 21:37:24 +01:00
translate_init.c	target-mips: Avoid shifting left into sign bit	2014-03-27 19:22:49 +04:00
translate.c	target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 mode	2014-03-25 23:36:35 +01:00