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d356312fdc
The env->pstate field is a little odd since it doesn't strictly speaking represent an architectural register. However it's convenient for QEMU to use it to hold the various PSTATE architectural bits in the same format the architecture specifies for SPSR registers (since this is the same format the kernel uses for signal handlers and the KVM register). Add some structure to how we deal with it: * document what env->pstate is * add some #defines for various bits in it * add helpers for reading/writing it taking account of caching of NZCV, and use them where appropriate * reset it on startup Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1385645602-18662-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
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* ARM gdb server stub: AArch64 specific functions.
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*
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "qemu-common.h"
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#include "exec/gdbstub.h"
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int aarch64_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (n < 31) {
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/* Core integer register. */
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return gdb_get_reg64(mem_buf, env->xregs[n]);
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}
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switch (n) {
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case 31:
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return gdb_get_reg64(mem_buf, env->xregs[31]);
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break;
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case 32:
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return gdb_get_reg64(mem_buf, env->pc);
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break;
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case 33:
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return gdb_get_reg32(mem_buf, pstate_read(env));
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}
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/* Unknown register. */
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return 0;
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}
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int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint64_t tmp;
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tmp = ldq_p(mem_buf);
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if (n < 31) {
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/* Core integer register. */
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env->xregs[n] = tmp;
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return 8;
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}
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switch (n) {
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case 31:
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env->xregs[31] = tmp;
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return 8;
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case 32:
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env->pc = tmp;
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return 8;
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case 33:
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/* CPSR */
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pstate_write(env, tmp);
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return 4;
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}
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/* Unknown register. */
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return 0;
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}
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