Rashmica Gupta 4b7f956862 hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 ... GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC. (Note that the ast2400 controller only goes up to group AB). A set has four groups (except set AC which only has one) and is referred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB). Each set is accessed and controlled by a bank of 14 registers. These registers operate on a per pin level where each bit in the register corresponds to a pin, except for the command source registers. The command source registers operate on a per group level where bits 24, 16, 8 and 0 correspond to each group in the set. eg. registers for set ABCD: |D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs |31...24|23...16|15....8|7.....0| <- bit position Note that there are a couple of groups that only have 4 pins. There are two ways that this model deviates from the behaviour of the actual controller: (1) The only control source driving the GPIO pins in the model is the ARM model (as there currently aren't models for the LPC or Coprocessor). (2) None of the registers in the model are reset tolerant (needs integration with the watchdog). Signed-off-by: Rashmica Gupta <rashmica.g@gmail.com> Tested-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20190904070506.1052-2-clg@kaod.org [clg: fixed missing header files made use of HWADDR_PRIx to fix compilation on windows ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2019-09-13 16:05:00 +01:00
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aspeed_gpio.h	hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500	2019-09-13 16:05:00 +01:00
bcm2835_gpio.h	include: Make headers more self-contained	2019-08-16 13:31:51 +02:00
imx_gpio.h	Clean up ill-advised or unusual header guards	2016-07-12 16:20:46 +02:00
nrf51_gpio.h	hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral	2019-01-07 15:23:47 +00:00