Bastian Koppelmann 6573777306 target/riscv: Fix sfence.vm/a both available in any priv version ... sfence.vm has been replaced in priv v1.10 spec by sfence.vma. Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-11-13 15:12:15 -08:00
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cpu_bits.h	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu_helper.c	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
cpu_user.h	RISC-V Linux User Emulation	2018-03-07 08:30:28 +13:00
cpu.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
cpu.h	RISC-V: Allow setting and clearing multiple irqs	2018-10-17 13:02:09 -07:00
fpu_helper.c	target/riscv: Remove floatX_maybe_silence_nan from conversions	2018-05-17 15:27:15 -07:00
gdbstub.c	RISC-V GDB Stub	2018-03-07 08:30:28 +13:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
Makefile.objs	RISC-V: Move non-ops from op_helper to cpu_helper	2018-10-17 13:02:14 -07:00
op_helper.c	RISC-V: Update CSR and interrupt definitions	2018-10-17 13:02:19 -07:00
pmp.c	target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64	2018-10-30 11:04:28 -07:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: Fix sfence.vm/a both available in any priv version	2018-11-13 15:12:15 -08:00