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c7a856b42e
Use the common API for semihosting logging. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200603123754.19059-4-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
184 lines
4.5 KiB
C
184 lines
4.5 KiB
C
/*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Contributions from 2012-04-01 on are considered under GPL version 2,
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* or (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "hw/semihosting/console.h"
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#undef DEBUG_UC32
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#ifdef DEBUG_UC32
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#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#ifndef CONFIG_USER_ONLY
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void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
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uint32_t cop)
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{
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/*
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* movc pp.nn, rn, #imm9
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* rn: UCOP_REG_D
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* nn: UCOP_REG_N
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* 1: sys control reg.
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* 2: page table base reg.
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* 3: data fault status reg.
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* 4: insn fault status reg.
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* 5: cache op. reg.
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* 6: tlb op. reg.
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* imm9: split UCOP_IMM10 with bit5 is 0
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*/
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switch (creg) {
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case 1:
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if (cop != 0) {
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goto unrecognized;
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}
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env->cp0.c1_sys = val;
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break;
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case 2:
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if (cop != 0) {
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goto unrecognized;
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}
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env->cp0.c2_base = val;
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break;
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case 3:
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if (cop != 0) {
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goto unrecognized;
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}
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env->cp0.c3_faultstatus = val;
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break;
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case 4:
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if (cop != 0) {
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goto unrecognized;
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}
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env->cp0.c4_faultaddr = val;
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break;
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case 5:
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switch (cop) {
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case 28:
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DPRINTF("Invalidate Entire I&D cache\n");
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return;
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case 20:
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DPRINTF("Invalidate Entire Icache\n");
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return;
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case 12:
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DPRINTF("Invalidate Entire Dcache\n");
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return;
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case 10:
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DPRINTF("Clean Entire Dcache\n");
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return;
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case 14:
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DPRINTF("Flush Entire Dcache\n");
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return;
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case 13:
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DPRINTF("Invalidate Dcache line\n");
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return;
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case 11:
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DPRINTF("Clean Dcache line\n");
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return;
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case 15:
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DPRINTF("Flush Dcache line\n");
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return;
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}
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break;
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case 6:
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if ((cop <= 6) && (cop >= 2)) {
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/* invalid all tlb */
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tlb_flush(env_cpu(env));
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return;
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}
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break;
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default:
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goto unrecognized;
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}
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return;
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unrecognized:
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qemu_log_mask(LOG_GUEST_ERROR,
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"Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
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creg, cop);
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}
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uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
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{
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/*
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* movc rd, pp.nn, #imm9
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* rd: UCOP_REG_D
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* nn: UCOP_REG_N
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* 0: cpuid and cachetype
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* 1: sys control reg.
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* 2: page table base reg.
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* 3: data fault status reg.
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* 4: insn fault status reg.
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* imm9: split UCOP_IMM10 with bit5 is 0
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*/
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switch (creg) {
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case 0:
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switch (cop) {
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case 0:
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return env->cp0.c0_cpuid;
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case 1:
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return env->cp0.c0_cachetype;
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}
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break;
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case 1:
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if (cop == 0) {
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return env->cp0.c1_sys;
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}
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break;
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case 2:
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if (cop == 0) {
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return env->cp0.c2_base;
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}
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break;
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case 3:
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if (cop == 0) {
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return env->cp0.c3_faultstatus;
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}
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break;
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case 4:
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if (cop == 0) {
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return env->cp0.c4_faultaddr;
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}
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break;
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
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creg, cop);
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return 0;
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}
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void helper_cp1_putc(target_ulong regval)
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{
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const char c = regval;
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qemu_semihosting_log_out(&c, sizeof(c));
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}
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#endif /* !CONFIG_USER_ONLY */
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bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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UniCore32CPU *cpu = UNICORE32_CPU(cs);
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CPUUniCore32State *env = &cpu->env;
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if (!(env->uncached_asr & ASR_I)) {
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cs->exception_index = UC32_EXCP_INTR;
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uc32_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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