mirror of
https://github.com/qemu/qemu.git
synced 2024-11-26 12:23:36 +08:00
b66f73a0cb
In SPI-mode, SD card's OCR register: Card Capacity Status (CCS) bit is not set to 1 correclty when the assigned SD image size is larger than 2GB (SDHC). This will cause the SD card to be indentified as SDSC incorrectly. CCS bit should be set to 1 if we are using SDHC. Also, as there's no power up emulation in SPI-mode. The OCR register: Card power up status bit bit (busy) should also be set to 1 when reset. (busy bit is set to LOW if the card has not finished the power up routine.) Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jim Shu <jim.shu@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211228125719.14712-1-frank.chang@sifive.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> |
||
---|---|---|
.. | ||
allwinner-sdhost.c | ||
aspeed_sdhci.c | ||
bcm2835_sdhost.c | ||
cadence_sdhci.c | ||
core.c | ||
Kconfig | ||
meson.build | ||
npcm7xx_sdhci.c | ||
omap_mmc.c | ||
pl181.c | ||
pxa2xx_mmci.c | ||
sd.c | ||
sdhci-internal.h | ||
sdhci-pci.c | ||
sdhci.c | ||
sdmmc-internal.c | ||
sdmmc-internal.h | ||
ssi-sd.c | ||
trace-events | ||
trace.h |