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25ee608d79
This commit fixes the difference reported in the bug in the reserved bit 52, it does this by adding this bit to the mask of bits to not be directly altered in the ppc_store_fpscr function (the hardware used to compare to QEMU was a Power9). The bits 0 to 27 were also added to the mask, as they are marked as reserved in the PowerISA and bit 28 is a reserved extension of the DRN field (bits 29:31) but can't be set using mtfsfi, while the other DRN bits may be set using mtfsfi instruction, so bit 28 was also added to the mask. Although this is a difference reported in the bug, since it's a reserved bit it may be a "don't care" case, as put in the bug report. Looking at the ISA it doesn't explicitly mention this bit can't be set, like it does for FEX and VX, so I'm unsure if this is necessary. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/266 Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20211201163808.440385-4-lucas.araujo@eldorado.org.br> Signed-off-by: Cédric Le Goater <clg@kaod.org>
127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/*
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* PowerPC CPU routines for qemu.
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*
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* Copyright (c) 2017 Nikunj A Dadhania, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu-models.h"
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#include "cpu-qom.h"
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#include "exec/log.h"
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#include "fpu/softfloat-helpers.h"
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#include "mmu-hash64.h"
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#include "helper_regs.h"
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#include "sysemu/tcg.h"
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target_ulong cpu_read_xer(const CPUPPCState *env)
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{
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if (is_isa300(env)) {
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return env->xer | (env->so << XER_SO) |
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(env->ov << XER_OV) | (env->ca << XER_CA) |
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(env->ov32 << XER_OV32) | (env->ca32 << XER_CA32);
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}
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return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) |
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(env->ca << XER_CA);
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}
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void cpu_write_xer(CPUPPCState *env, target_ulong xer)
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{
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env->so = (xer >> XER_SO) & 1;
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env->ov = (xer >> XER_OV) & 1;
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env->ca = (xer >> XER_CA) & 1;
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/* write all the flags, while reading back check of isa300 */
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env->ov32 = (xer >> XER_OV32) & 1;
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env->ca32 = (xer >> XER_CA32) & 1;
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env->xer = xer & ~((1ul << XER_SO) |
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(1ul << XER_OV) | (1ul << XER_CA) |
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(1ul << XER_OV32) | (1ul << XER_CA32));
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}
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void ppc_store_vscr(CPUPPCState *env, uint32_t vscr)
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{
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env->vscr = vscr & ~(1u << VSCR_SAT);
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/* Which bit we set is completely arbitrary, but clear the rest. */
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env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT);
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env->vscr_sat.u64[1] = 0;
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set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status);
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}
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uint32_t ppc_get_vscr(CPUPPCState *env)
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{
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uint32_t sat = (env->vscr_sat.u64[0] | env->vscr_sat.u64[1]) != 0;
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return env->vscr | (sat << VSCR_SAT);
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}
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/* GDBstub can read and write MSR... */
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void ppc_store_msr(CPUPPCState *env, target_ulong value)
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{
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hreg_store_msr(env, value, 0);
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}
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void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val)
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{
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PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
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CPUPPCState *env = &cpu->env;
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env->spr[SPR_LPCR] = val & pcc->lpcr_mask;
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/* The gtse bit affects hflags */
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hreg_compute_hflags(env);
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}
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static inline void fpscr_set_rounding_mode(CPUPPCState *env)
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{
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int rnd_type;
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/* Set rounding mode */
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switch (fpscr_rn) {
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case 0:
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/* Best approximation (round to nearest) */
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rnd_type = float_round_nearest_even;
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break;
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case 1:
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/* Smaller magnitude (round toward zero) */
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rnd_type = float_round_to_zero;
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break;
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case 2:
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/* Round toward +infinite */
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rnd_type = float_round_up;
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break;
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default:
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case 3:
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/* Round toward -infinite */
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rnd_type = float_round_down;
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break;
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}
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set_float_rounding_mode(rnd_type, &env->fp_status);
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}
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void ppc_store_fpscr(CPUPPCState *env, target_ulong val)
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{
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val &= FPSCR_MTFS_MASK;
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if (val & FPSCR_IX) {
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val |= FP_VX;
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}
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if ((val >> FPSCR_XX) & (val >> FPSCR_XE) & 0x1f) {
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val |= FP_FEX;
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}
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env->fpscr = val;
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if (tcg_enabled()) {
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fpscr_set_rounding_mode(env);
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}
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}
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