qemu/target/mips
Yongbok Kim 5e31fdd59f target/mips: Add CP0 PWBase register
Add PWBase register (CP0 Register 5, Select 5).

The PWBase register contains the Page Table Base virtual address.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-10-18 20:37:20 +02:00
..
cp0_timer.c mips: introduce internal.h and cleanup cpu.h 2017-09-21 13:24:34 +01:00
cpu-qom.h mips: MIPSCPU model subclasses 2017-09-21 13:25:30 +01:00
cpu.c qdev: use device_class_set_parent_realize/unrealize/reset() 2018-02-05 13:54:38 +01:00
cpu.h target/mips: Add CP0 PWBase register 2018-10-18 20:37:20 +02:00
dsp_helper.c Remove unnecessary variables for function return value 2018-05-20 08:48:13 +03:00
gdbstub.c target/mips: Fix gdbstub to read/write 64 bit FP registers 2018-06-27 20:13:50 +02:00
helper.c target/mips: Add updating BadInstr and BadInstrX for nanoMIPS 2018-08-24 17:51:59 +02:00
helper.h target/mips: Implement emulation of nanoMIPS ROTX instruction 2018-08-24 17:51:59 +02:00
internal.h target/mips: Improve DSP R2/R3-related naming 2018-10-18 20:37:20 +02:00
kvm_mips.h
kvm.c mips: introduce internal.h and cleanup cpu.h 2017-09-21 13:24:34 +01:00
lmi_helper.c
machine.c target/mips: Add CP0 PWBase register 2018-10-18 20:37:20 +02:00
Makefile.objs mips: move hw/mips/cputimer.c to target/mips/ 2017-09-21 13:24:34 +01:00
mips-defs.h target/mips: Improve DSP R2/R3-related naming 2018-10-18 20:37:20 +02:00
mips-semi.c
msa_helper.c target/mips: Remove floatX_maybe_silence_nan from conversions 2018-05-17 15:27:15 -07:00
op_helper.c target/mips: Fix ERET/ERETNC behavior related to ADEL exception 2018-08-24 17:51:59 +02:00
TODO
trace-events docs: fix broken paths to docs/devel/tracing.txt 2017-07-31 13:12:53 +03:00
translate_init.inc.c target/mips: Improve DSP R2/R3-related naming 2018-10-18 20:37:20 +02:00
translate.c target/mips: Add CP0 PWBase register 2018-10-18 20:37:20 +02:00