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55236da222
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David Hildenbrand 55236da222 s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL 
Take care of properly taking the modulo of the count. We might later
want to come back and create a variant of VERLL where the base register
is 0, resulting in an immediate.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17 10:54:13 +02:00
..
alpha tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
arm Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
cris Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
hppa tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
i386 Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
lm32 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
m68k tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
microblaze tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
mips tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
moxie tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
nios2 Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
openrisc tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
ppc Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
riscv Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
s390x s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL 2019-05-17 10:54:13 +02:00
sh4 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
sparc Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
tilegx target/tilegx: Convert to CPUClass::tlb_fill 2019-05-10 11:12:50 -07:00
tricore Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00
unicore32 tcg: Use CPUClass::tlb_fill in cputlb.c 2019-05-10 11:12:50 -07:00
xtensa Add CPUClass::tlb_fill. 2019-05-16 13:15:08 +01:00