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323 lines
8.1 KiB
C
323 lines
8.1 KiB
C
/*
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* IMX31 Clock Control Module
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*
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* Copyright (C) 2012 NICTA
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* To get the timer frequencies right, we need to emulate at least part of
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* the CCM.
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*/
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/arm/imx.h"
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#define CKIH_FREQ 26000000 /* 26MHz crystal input */
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#define CKIL_FREQ 32768 /* nominal 32khz clock */
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//#define DEBUG_CCM 1
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#ifdef DEBUG_CCM
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#define DPRINTF(fmt, args...) \
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do { printf("imx_ccm: " fmt , ##args); } while (0)
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#else
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#define DPRINTF(fmt, args...) do {} while (0)
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#endif
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static int imx_ccm_post_load(void *opaque, int version_id);
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t ccmr;
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uint32_t pdr0;
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uint32_t pdr1;
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uint32_t mpctl;
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uint32_t spctl;
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uint32_t cgr[3];
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uint32_t pmcr0;
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uint32_t pmcr1;
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/* Frequencies precalculated on register changes */
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uint32_t pll_refclk_freq;
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uint32_t mcu_clk_freq;
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uint32_t hsp_clk_freq;
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uint32_t ipg_clk_freq;
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} IMXCCMState;
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static const VMStateDescription vmstate_imx_ccm = {
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.name = "imx-ccm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ccmr, IMXCCMState),
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VMSTATE_UINT32(pdr0, IMXCCMState),
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VMSTATE_UINT32(pdr1, IMXCCMState),
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VMSTATE_UINT32(mpctl, IMXCCMState),
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VMSTATE_UINT32(spctl, IMXCCMState),
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VMSTATE_UINT32_ARRAY(cgr, IMXCCMState, 3),
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VMSTATE_UINT32(pmcr0, IMXCCMState),
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VMSTATE_UINT32(pmcr1, IMXCCMState),
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VMSTATE_UINT32(pll_refclk_freq, IMXCCMState),
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},
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.post_load = imx_ccm_post_load,
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};
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/* CCMR */
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#define CCMR_FPME (1<<0)
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#define CCMR_MPE (1<<3)
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#define CCMR_MDS (1<<7)
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#define CCMR_FPMF (1<<26)
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#define CCMR_PRCS (3<<1)
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/* PDR0 */
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#define PDR0_MCU_PODF_SHIFT (0)
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#define PDR0_MCU_PODF_MASK (0x7)
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#define PDR0_MAX_PODF_SHIFT (3)
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#define PDR0_MAX_PODF_MASK (0x7)
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#define PDR0_IPG_PODF_SHIFT (6)
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#define PDR0_IPG_PODF_MASK (0x3)
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#define PDR0_NFC_PODF_SHIFT (8)
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#define PDR0_NFC_PODF_MASK (0x7)
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#define PDR0_HSP_PODF_SHIFT (11)
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#define PDR0_HSP_PODF_MASK (0x7)
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#define PDR0_PER_PODF_SHIFT (16)
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#define PDR0_PER_PODF_MASK (0x1f)
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#define PDR0_CSI_PODF_SHIFT (23)
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#define PDR0_CSI_PODF_MASK (0x1ff)
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#define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
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& PDR0_##name##_PODF_MASK)
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#define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
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PDR0_##name##_PODF_SHIFT)
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/* PLL control registers */
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#define PD(v) (((v) >> 26) & 0xf)
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#define MFD(v) (((v) >> 16) & 0x3ff)
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#define MFI(v) (((v) >> 10) & 0xf);
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#define MFN(v) ((v) & 0x3ff)
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#define PLL_PD(x) (((x) & 0xf) << 26)
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#define PLL_MFD(x) (((x) & 0x3ff) << 16)
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#define PLL_MFI(x) (((x) & 0xf) << 10)
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#define PLL_MFN(x) (((x) & 0x3ff) << 0)
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uint32_t imx_clock_frequency(DeviceState *dev, IMXClk clock)
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{
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IMXCCMState *s = container_of(dev, IMXCCMState, busdev.qdev);
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switch (clock) {
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case NOCLK:
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return 0;
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case MCU:
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return s->mcu_clk_freq;
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case HSP:
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return s->hsp_clk_freq;
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case IPG:
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return s->ipg_clk_freq;
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case CLK_32k:
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return CKIL_FREQ;
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}
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return 0;
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}
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/*
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* Calculate PLL output frequency
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*/
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static uint32_t calc_pll(uint32_t pllreg, uint32_t base_freq)
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{
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int32_t mfn = MFN(pllreg); /* Numerator */
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uint32_t mfi = MFI(pllreg); /* Integer part */
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uint32_t mfd = 1 + MFD(pllreg); /* Denominator */
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uint32_t pd = 1 + PD(pllreg); /* Pre-divider */
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if (mfi < 5) {
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mfi = 5;
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}
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/* mfn is 10-bit signed twos-complement */
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mfn <<= 32 - 10;
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mfn >>= 32 - 10;
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return ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
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(mfd * pd)) << 10;
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}
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static void update_clocks(IMXCCMState *s)
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{
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/*
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* If we ever emulate more clocks, this should switch to a data-driven
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* approach
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*/
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if ((s->ccmr & CCMR_PRCS) == 2) {
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s->pll_refclk_freq = CKIL_FREQ * 1024;
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} else {
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s->pll_refclk_freq = CKIH_FREQ;
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}
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/* ipg_clk_arm aka MCU clock */
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if ((s->ccmr & CCMR_MDS) || !(s->ccmr & CCMR_MPE)) {
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s->mcu_clk_freq = s->pll_refclk_freq;
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} else {
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s->mcu_clk_freq = calc_pll(s->mpctl, s->pll_refclk_freq);
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}
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/* High-speed clock */
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s->hsp_clk_freq = s->mcu_clk_freq / (1 + EXTRACT(s->pdr0, HSP));
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s->ipg_clk_freq = s->hsp_clk_freq / (1 + EXTRACT(s->pdr0, IPG));
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DPRINTF("Clocks: mcu %uMHz, HSP %uMHz, IPG %uHz\n",
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s->mcu_clk_freq / 1000000,
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s->hsp_clk_freq / 1000000,
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s->ipg_clk_freq);
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}
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static void imx_ccm_reset(DeviceState *dev)
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{
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IMXCCMState *s = container_of(dev, IMXCCMState, busdev.qdev);
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s->ccmr = 0x074b0b7b;
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s->pdr0 = 0xff870b48;
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s->pdr1 = 0x49fcfe7f;
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s->mpctl = PLL_PD(1) | PLL_MFD(0) | PLL_MFI(6) | PLL_MFN(0);
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s->cgr[0] = s->cgr[1] = s->cgr[2] = 0xffffffff;
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s->spctl = PLL_PD(1) | PLL_MFD(4) | PLL_MFI(0xc) | PLL_MFN(1);
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s->pmcr0 = 0x80209828;
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update_clocks(s);
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}
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static uint64_t imx_ccm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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IMXCCMState *s = (IMXCCMState *)opaque;
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DPRINTF("read(offset=%x)", offset >> 2);
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switch (offset >> 2) {
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case 0: /* CCMR */
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DPRINTF(" ccmr = 0x%x\n", s->ccmr);
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return s->ccmr;
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case 1:
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DPRINTF(" pdr0 = 0x%x\n", s->pdr0);
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return s->pdr0;
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case 2:
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DPRINTF(" pdr1 = 0x%x\n", s->pdr1);
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return s->pdr1;
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case 4:
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DPRINTF(" mpctl = 0x%x\n", s->mpctl);
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return s->mpctl;
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case 6:
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DPRINTF(" spctl = 0x%x\n", s->spctl);
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return s->spctl;
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case 8:
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DPRINTF(" cgr0 = 0x%x\n", s->cgr[0]);
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return s->cgr[0];
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case 9:
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DPRINTF(" cgr1 = 0x%x\n", s->cgr[1]);
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return s->cgr[1];
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case 10:
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DPRINTF(" cgr2 = 0x%x\n", s->cgr[2]);
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return s->cgr[2];
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case 18: /* LTR1 */
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return 0x00004040;
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case 23:
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DPRINTF(" pcmr0 = 0x%x\n", s->pmcr0);
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return s->pmcr0;
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}
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DPRINTF(" return 0\n");
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return 0;
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}
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static void imx_ccm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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IMXCCMState *s = (IMXCCMState *)opaque;
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DPRINTF("write(offset=%x, value = %x)\n",
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offset >> 2, (unsigned int)value);
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switch (offset >> 2) {
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case 0:
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s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
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break;
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case 1:
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s->pdr0 = value & 0xff9f3fff;
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break;
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case 2:
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s->pdr1 = value;
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break;
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case 4:
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s->mpctl = value & 0xbfff3fff;
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break;
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case 6:
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s->spctl = value & 0xbfff3fff;
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break;
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case 8:
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s->cgr[0] = value;
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return;
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case 9:
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s->cgr[1] = value;
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return;
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case 10:
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s->cgr[2] = value;
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return;
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default:
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return;
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}
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update_clocks(s);
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}
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static const struct MemoryRegionOps imx_ccm_ops = {
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.read = imx_ccm_read,
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.write = imx_ccm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int imx_ccm_init(SysBusDevice *dev)
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{
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IMXCCMState *s = FROM_SYSBUS(typeof(*s), dev);
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memory_region_init_io(&s->iomem, OBJECT(dev), &imx_ccm_ops, s,
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"imx_ccm", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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static int imx_ccm_post_load(void *opaque, int version_id)
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{
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IMXCCMState *s = (IMXCCMState *)opaque;
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update_clocks(s);
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return 0;
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}
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static void imx_ccm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
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sbc->init = imx_ccm_init;
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dc->reset = imx_ccm_reset;
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dc->vmsd = &vmstate_imx_ccm;
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dc->desc = "i.MX Clock Control Module";
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}
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static const TypeInfo imx_ccm_info = {
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.name = "imx_ccm",
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXCCMState),
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.class_init = imx_ccm_class_init,
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};
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static void imx_ccm_register_types(void)
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{
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type_register_static(&imx_ccm_info);
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}
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type_init(imx_ccm_register_types)
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