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qemu/target/arm
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Shuuichirou Ishii e31c70ac04 target-arm: Add support for Fujitsu A64FX 
Add a definition for the Fujitsu A64FX processor.

The A64FX processor does not implement the AArch32 Execution state,
so there are no associated AArch32 Identification registers.

For SVE, the A64FX processor supports only 128,256 and 512bit vector
lengths.

The Identification register values are defined based on the FX700,
and have been tested and confirmed.

Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-09-01 11:08:18 +01:00
..
a32-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
a32.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arch_dump.c target/arm: add spaces around operator 2020-11-10 11:03:47 +00:00
arm_ldst.h arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
arm-powerctl.c arm/arm-powerctl: rebuild hflags after setting CP15 bits in arm_set_cpu_on() 2019-12-20 14:03:00 +00:00
arm-powerctl.h target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset() 2019-02-28 11:03:04 +00:00
cpu64.c target-arm: Add support for Fujitsu A64FX 2021-09-01 11:08:18 +01:00
cpu_tcg.c target/arm: Enable MVE in Cortex-M55 2021-09-01 11:08:18 +01:00
cpu-param.h linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE 2021-02-16 13:06:16 +00:00
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c target/arm: Avoid assertion trying to use KVM and multiple ASes 2021-08-26 17:02:01 +01:00
cpu.h target/arm: Do hflags rebuild in cpsr_write() 2021-08-26 17:02:01 +01:00
crypto_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
debug_helper.c accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
gdbstub64.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
gdbstub.c target/arm: Enforce that M-profile SP low 2 bits are always zero 2021-07-27 10:57:39 +01:00
helper-a64.c tcg: Rename helper_atomic_*_mmu and provide for user-only 2021-07-21 07:45:38 -10:00
helper-a64.h target/arm: Merge mte_check1, mte_checkN 2021-04-30 11:16:49 +01:00
helper-mve.h target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
helper-sve.h target/arm: Implement vector float32 to bfloat16 conversion 2021-06-03 16:43:26 +01:00
helper.c target/arm: Do hflags rebuild in cpsr_write() 2021-08-26 17:02:01 +01:00
helper.h target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
idau.h Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
internals.h target/arm: Export aarch64_sve_zcr_get_valid_len 2021-07-27 10:57:40 +01:00
iwmmxt_helper.c arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm64.c target/arm/kvm64: Ensure sve vls map is completely clear 2021-08-26 17:01:59 +01:00
kvm_arm.h hw/arm/virt: KVM: The IPA lower bound is 32 2021-03-12 12:47:11 +00:00
kvm-consts.h target/arm: Remove no-longer-reachable 32-bit KVM code 2020-09-14 14:23:19 +01:00
kvm-stub.c Include qemu-common.h exactly where needed 2019-06-12 13:20:20 +02:00
kvm.c target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route() 2021-08-25 10:48:50 +01:00
m_helper.c target/arm: Implement M-profile trapping on division by zero 2021-08-25 10:48:50 +01:00
m-nocp.decode target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00
machine.c target/arm: Make FPSCR.LTPSIZE writable for MVE 2021-06-03 16:43:25 +01:00
meson.build target/arm: Implement MVE VLDR/VSTR (non-widening forms) 2021-06-21 16:49:38 +01:00
monitor.c target/arm: Add cpu properties to control pauth 2021-01-19 14:38:51 +00:00
mte_helper.c target/arm: Implement MTE3 2021-06-24 14:58:48 +01:00
mve_helper.c target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
mve.decode target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
neon_helper.c target/arm: Split out saturating/rounding shifts from neon 2021-05-25 16:01:43 +01:00
neon-dp.decode target/arm: Implement vector float32 to bfloat16 conversion 2021-06-03 16:43:26 +01:00
neon-ls.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
neon-shared.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
op_addsub.h
op_helper.c target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
pauth_helper.c target/arm: Implement an IMPDEF pauth algorithm 2021-01-19 14:38:51 +00:00
psci.c sysemu: Split sysemu/runstate.h off sysemu/sysemu.h 2019-08-16 13:37:36 +02:00
sve_helper.c bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations 2021-06-16 14:33:52 +01:00
sve.decode target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
syndrome.h target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
t16.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
t32.decode target/arm: Implement MVE VCTP 2021-08-25 10:48:50 +01:00
tlb_helper.c target/arm: Set ARMMMUFaultInfo.level in user-only arm_cpu_tlb_fill 2021-03-23 14:07:55 +00:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate-a32.h target/arm: Implement MVE VCTP 2021-08-25 10:48:50 +01:00
translate-a64.c accel/tcg: Remove TranslatorOps.breakpoint_check 2021-07-21 07:47:05 -10:00
translate-a64.h target/arm: Implement SVE2 XAR 2021-05-25 16:01:44 +01:00
translate-m-nocp.c target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() 2021-06-21 16:49:38 +01:00
translate-mve.c target/arm: Implement MVE VRINT insns 2021-09-01 11:08:17 +01:00
translate-neon.c target/arm: Implement MVE VADD (floating-point) 2021-09-01 11:08:16 +01:00
translate-sve.c target/arm: Remove duplicate 'plus1' function from Neon and SVE decode 2021-07-18 10:59:47 +01:00
translate-vfp.c target/arm: Implement MVE VMOV to/from 2 general-purpose registers 2021-08-25 10:48:50 +01:00
translate.c target/arm: Implement HSTR.TJDBX 2021-08-26 17:02:01 +01:00
translate.h target/arm: Implement MVE VADD (floating-point) 2021-09-01 11:08:16 +01:00
vec_helper.c target/arm: Implement MVE VMULL (polynomial) 2021-08-25 10:48:49 +01:00
vec_internal.h target/arm: Implement MVE VMULL (polynomial) 2021-08-25 10:48:49 +01:00
vfp_helper.c target/arm: Check NaN mode before silencing NaN 2021-07-02 11:48:36 +01:00
vfp-uncond.decode arm tcg cpus: Fix Lesser GPL version number 2020-11-15 16:42:14 +01:00
vfp.decode target/arm: Don't NOCP fault for FPCXT_NS accesses 2021-06-21 16:49:37 +01:00