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0b8fa32f55
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
204 lines
5.2 KiB
C
204 lines
5.2 KiB
C
/*
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* QEMU PowerPC PowerNV Interrupt Control Presenter (ICP) model
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*
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* Copyright (c) 2017, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License
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* as published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "sysemu/sysemu.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/ppc/xics.h"
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#define ICP_XIRR_POLL 0 /* 1 byte (CPRR) or 4 bytes */
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#define ICP_XIRR 4 /* 1 byte (CPRR) or 4 bytes */
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#define ICP_MFRR 12 /* 1 byte access only */
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#define ICP_LINKA 16 /* unused */
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#define ICP_LINKB 20 /* unused */
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#define ICP_LINKC 24 /* unused */
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static uint64_t pnv_icp_read(void *opaque, hwaddr addr, unsigned width)
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{
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ICPState *icp = ICP(opaque);
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PnvICPState *picp = PNV_ICP(opaque);
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bool byte0 = (width == 1 && (addr & 0x3) == 0);
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uint64_t val = 0xffffffff;
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switch (addr & 0xffc) {
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case ICP_XIRR_POLL:
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val = icp_ipoll(icp, NULL);
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if (byte0) {
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val >>= 24;
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} else if (width != 4) {
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goto bad_access;
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}
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break;
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case ICP_XIRR:
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if (byte0) {
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val = icp_ipoll(icp, NULL) >> 24;
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} else if (width == 4) {
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val = icp_accept(icp);
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} else {
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goto bad_access;
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}
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break;
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case ICP_MFRR:
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if (byte0) {
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val = icp->mfrr;
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} else {
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goto bad_access;
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}
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break;
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case ICP_LINKA:
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if (width == 4) {
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val = picp->links[0];
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} else {
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goto bad_access;
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}
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break;
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case ICP_LINKB:
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if (width == 4) {
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val = picp->links[1];
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} else {
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goto bad_access;
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}
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break;
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case ICP_LINKC:
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if (width == 4) {
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val = picp->links[2];
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} else {
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goto bad_access;
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}
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break;
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default:
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bad_access:
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qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%"
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HWADDR_PRIx"/%d\n", addr, width);
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}
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return val;
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}
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static void pnv_icp_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned width)
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{
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ICPState *icp = ICP(opaque);
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PnvICPState *picp = PNV_ICP(opaque);
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bool byte0 = (width == 1 && (addr & 0x3) == 0);
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switch (addr & 0xffc) {
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case ICP_XIRR:
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if (byte0) {
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icp_set_cppr(icp, val);
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} else if (width == 4) {
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icp_eoi(icp, val);
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} else {
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goto bad_access;
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}
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break;
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case ICP_MFRR:
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if (byte0) {
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icp_set_mfrr(icp, val);
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} else {
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goto bad_access;
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}
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break;
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case ICP_LINKA:
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if (width == 4) {
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picp->links[0] = val;
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} else {
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goto bad_access;
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}
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break;
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case ICP_LINKB:
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if (width == 4) {
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picp->links[1] = val;
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} else {
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goto bad_access;
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}
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break;
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case ICP_LINKC:
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if (width == 4) {
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picp->links[2] = val;
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} else {
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goto bad_access;
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}
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break;
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default:
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bad_access:
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qemu_log_mask(LOG_GUEST_ERROR, "XICS: Bad ICP access 0x%"
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HWADDR_PRIx"/%d\n", addr, width);
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}
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}
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static const MemoryRegionOps pnv_icp_ops = {
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.read = pnv_icp_read,
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.write = pnv_icp_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void pnv_icp_realize(DeviceState *dev, Error **errp)
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{
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ICPState *icp = ICP(dev);
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PnvICPState *pnv_icp = PNV_ICP(icp);
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ICPStateClass *icpc = ICP_GET_CLASS(icp);
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Error *local_err = NULL;
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icpc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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memory_region_init_io(&pnv_icp->mmio, OBJECT(icp), &pnv_icp_ops,
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icp, "icp-thread", 0x1000);
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}
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static void pnv_icp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ICPStateClass *icpc = ICP_CLASS(klass);
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device_class_set_parent_realize(dc, pnv_icp_realize,
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&icpc->parent_realize);
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dc->desc = "PowerNV ICP";
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}
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static const TypeInfo pnv_icp_info = {
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.name = TYPE_PNV_ICP,
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.parent = TYPE_ICP,
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.instance_size = sizeof(PnvICPState),
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.class_init = pnv_icp_class_init,
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.class_size = sizeof(ICPStateClass),
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};
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static void pnv_icp_register_types(void)
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{
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type_register_static(&pnv_icp_info);
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}
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type_init(pnv_icp_register_types)
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