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4f67d30b5e
The following patch will need to handle properties registration during class_init time. Let's use a device_class_set_props() setter. spatch --macro-file scripts/cocci-macro-file.h --sp-file ./scripts/coccinelle/qdev-set-props.cocci --keep-comments --in-place --dir . @@ typedef DeviceClass; DeviceClass *d; expression val; @@ - d->props = val + device_class_set_props(d, val) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20200110153039.1379601-20-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
256 lines
7.6 KiB
C
256 lines
7.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*
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* Copyright (C) 2015 Imagination Technologies
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/misc/mips_cmgcr.h"
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#include "hw/misc/mips_cpc.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/mips_gic.h"
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static inline bool is_cpc_connected(MIPSGCRState *s)
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{
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return s->cpc_mr != NULL;
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}
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static inline bool is_gic_connected(MIPSGCRState *s)
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{
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return s->gic_mr != NULL;
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}
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static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val)
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{
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CPUState *cpu;
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MIPSCPU *mips_cpu;
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gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK;
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memory_region_set_address(&gcr->iomem, gcr->gcr_base);
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CPU_FOREACH(cpu) {
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mips_cpu = MIPS_CPU(cpu);
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mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4;
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}
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}
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static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
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{
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if (is_cpc_connected(gcr)) {
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gcr->cpc_base = val & GCR_CPC_BASE_MSK;
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memory_region_transaction_begin();
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memory_region_set_address(gcr->cpc_mr,
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gcr->cpc_base & GCR_CPC_BASE_CPCBASE_MSK);
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memory_region_set_enabled(gcr->cpc_mr,
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gcr->cpc_base & GCR_CPC_BASE_CPCEN_MSK);
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memory_region_transaction_commit();
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}
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}
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static inline void update_gic_base(MIPSGCRState *gcr, uint64_t val)
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{
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if (is_gic_connected(gcr)) {
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gcr->gic_base = val & GCR_GIC_BASE_MSK;
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memory_region_transaction_begin();
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memory_region_set_address(gcr->gic_mr,
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gcr->gic_base & GCR_GIC_BASE_GICBASE_MSK);
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memory_region_set_enabled(gcr->gic_mr,
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gcr->gic_base & GCR_GIC_BASE_GICEN_MSK);
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memory_region_transaction_commit();
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}
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}
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/* Read GCR registers */
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static uint64_t gcr_read(void *opaque, hwaddr addr, unsigned size)
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{
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MIPSGCRState *gcr = (MIPSGCRState *) opaque;
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MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index];
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MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
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switch (addr) {
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/* Global Control Block Register */
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case GCR_CONFIG_OFS:
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/* Set PCORES to 0 */
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return 0;
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case GCR_BASE_OFS:
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return gcr->gcr_base;
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case GCR_REV_OFS:
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return gcr->gcr_rev;
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case GCR_GIC_BASE_OFS:
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return gcr->gic_base;
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case GCR_CPC_BASE_OFS:
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return gcr->cpc_base;
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case GCR_GIC_STATUS_OFS:
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return is_gic_connected(gcr);
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case GCR_CPC_STATUS_OFS:
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return is_cpc_connected(gcr);
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case GCR_L2_CONFIG_OFS:
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/* L2 BYPASS */
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return GCR_L2_CONFIG_BYPASS_MSK;
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/* Core-Local and Core-Other Control Blocks */
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case MIPS_CLCB_OFS + GCR_CL_CONFIG_OFS:
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case MIPS_COCB_OFS + GCR_CL_CONFIG_OFS:
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/* Set PVP to # of VPs - 1 */
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return gcr->num_vps - 1;
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case MIPS_CLCB_OFS + GCR_CL_RESETBASE_OFS:
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return current_vps->reset_base;
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case MIPS_COCB_OFS + GCR_CL_RESETBASE_OFS:
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return other_vps->reset_base;
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case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:
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return current_vps->other;
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case MIPS_COCB_OFS + GCR_CL_OTHER_OFS:
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return other_vps->other;
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default:
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qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx
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"\n", size, addr);
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return 0;
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}
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return 0;
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}
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static inline target_ulong get_exception_base(MIPSGCRVPState *vps)
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{
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/* TODO: BEV_BASE and SELECT_BEV */
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return (int32_t)(vps->reset_base & GCR_CL_RESET_BASE_RESETBASE_MSK);
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}
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/* Write GCR registers */
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static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
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{
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MIPSGCRState *gcr = (MIPSGCRState *)opaque;
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MIPSGCRVPState *current_vps = &gcr->vps[current_cpu->cpu_index];
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MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
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switch (addr) {
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case GCR_BASE_OFS:
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update_gcr_base(gcr, data);
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break;
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case GCR_GIC_BASE_OFS:
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update_gic_base(gcr, data);
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break;
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case GCR_CPC_BASE_OFS:
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update_cpc_base(gcr, data);
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break;
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case MIPS_CLCB_OFS + GCR_CL_RESETBASE_OFS:
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current_vps->reset_base = data & GCR_CL_RESET_BASE_MSK;
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cpu_set_exception_base(current_cpu->cpu_index,
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get_exception_base(current_vps));
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break;
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case MIPS_COCB_OFS + GCR_CL_RESETBASE_OFS:
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other_vps->reset_base = data & GCR_CL_RESET_BASE_MSK;
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cpu_set_exception_base(current_vps->other,
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get_exception_base(other_vps));
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break;
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case MIPS_CLCB_OFS + GCR_CL_OTHER_OFS:
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if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) {
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current_vps->other = data & GCR_CL_OTHER_MSK;
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}
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break;
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case MIPS_COCB_OFS + GCR_CL_OTHER_OFS:
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if ((data & GCR_CL_OTHER_MSK) < gcr->num_vps) {
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other_vps->other = data & GCR_CL_OTHER_MSK;
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx
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" 0x%" PRIx64 "\n", size, addr, data);
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break;
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}
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}
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static const MemoryRegionOps gcr_ops = {
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.read = gcr_read,
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.write = gcr_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.max_access_size = 8,
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},
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};
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static void mips_gcr_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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MIPSGCRState *s = MIPS_GCR(obj);
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memory_region_init_io(&s->iomem, OBJECT(s), &gcr_ops, s,
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"mips-gcr", GCR_ADDRSPACE_SZ);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void mips_gcr_reset(DeviceState *dev)
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{
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MIPSGCRState *s = MIPS_GCR(dev);
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int i;
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update_gic_base(s, 0);
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update_cpc_base(s, 0);
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for (i = 0; i < s->num_vps; i++) {
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s->vps[i].other = 0;
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s->vps[i].reset_base = 0xBFC00000 & GCR_CL_RESET_BASE_MSK;
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cpu_set_exception_base(i, get_exception_base(&s->vps[i]));
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}
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}
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static const VMStateDescription vmstate_mips_gcr = {
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.name = "mips-gcr",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT64(cpc_base, MIPSGCRState),
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VMSTATE_END_OF_LIST()
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},
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};
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static Property mips_gcr_properties[] = {
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DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1),
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DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800),
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DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR),
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DEFINE_PROP_LINK("gic", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_LINK("cpc", MIPSGCRState, cpc_mr, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void mips_gcr_realize(DeviceState *dev, Error **errp)
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{
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MIPSGCRState *s = MIPS_GCR(dev);
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/* Create local set of registers for each VP */
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s->vps = g_new(MIPSGCRVPState, s->num_vps);
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}
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static void mips_gcr_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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device_class_set_props(dc, mips_gcr_properties);
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dc->vmsd = &vmstate_mips_gcr;
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dc->reset = mips_gcr_reset;
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dc->realize = mips_gcr_realize;
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}
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static const TypeInfo mips_gcr_info = {
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.name = TYPE_MIPS_GCR,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MIPSGCRState),
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.instance_init = mips_gcr_init,
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.class_init = mips_gcr_class_init,
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};
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static void mips_gcr_register_types(void)
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{
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type_register_static(&mips_gcr_info);
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}
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type_init(mips_gcr_register_types)
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