mirror of
https://github.com/qemu/qemu.git
synced 2024-12-11 12:43:55 +08:00
fcf5ef2ab5
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
52 lines
1.9 KiB
Plaintext
52 lines
1.9 KiB
Plaintext
Unsolved issues/bugs in the mips/mipsel backend
|
|
-----------------------------------------------
|
|
|
|
General
|
|
-------
|
|
- Unimplemented ASEs:
|
|
- MDMX
|
|
- SmartMIPS
|
|
- microMIPS DSP r1 & r2 encodings
|
|
- MT ASE only partially implemented and not functional
|
|
- Shadow register support only partially implemented,
|
|
lacks set switching on interrupt/exception.
|
|
- 34K ITC not implemented.
|
|
- A general lack of documentation, especially for technical internals.
|
|
Existing documentation is x86-centric.
|
|
- Reverse endianness bit not implemented
|
|
- The TLB emulation is very inefficient:
|
|
QEMU's softmmu implements a x86-style MMU, with separate entries
|
|
for read/write/execute, a TLB index which is just a modulo of the
|
|
virtual address, and a set of TLBs for each user/kernel/supervisor
|
|
MMU mode.
|
|
MIPS has a single entry for read/write/execute and only one MMU mode.
|
|
But it is fully associative with randomized entry indices, and uses
|
|
up to 256 ASID tags as additional matching criterion (which roughly
|
|
equates to 256 MMU modes). It also has a global flag which causes
|
|
entries to match regardless of ASID.
|
|
To cope with these differences, QEMU currently flushes the TLB at
|
|
each ASID change. Using the MMU modes to implement ASIDs hinges on
|
|
implementing the global bit efficiently.
|
|
- save/restore of the CPU state is not implemented (see machine.c).
|
|
|
|
MIPS64
|
|
------
|
|
- Userland emulation (both n32 and n64) not functional.
|
|
|
|
"Generic" 4Kc system emulation
|
|
------------------------------
|
|
- Doesn't correspond to any real hardware. Should be removed some day,
|
|
U-Boot is the last remaining user.
|
|
|
|
PICA 61 system emulation
|
|
------------------------
|
|
- No framebuffer support yet.
|
|
|
|
MALTA system emulation
|
|
----------------------
|
|
- We fake firmware support instead of doing the real thing
|
|
- Real firmware (YAMON) falls over when trying to init RAM, presumably
|
|
due to lacking system controller emulation.
|
|
- Bonito system controller not implemented
|
|
- MSC1 system controller not implemented
|