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* Implement fp16 support for AArch32 VFP and Neon * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes * hw/arm/sbsa-ref : Add embedded controller in secure memory -----BEGIN PGP SIGNATURE----- iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAl9OZgMZHHBldGVyLm1h eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3uRfD/4kjn9wRlcHJkFYajL6nk1f 6CI8CAeb6Fv2+snzcDfbutqC1jdL2V9qeojsq6K1L/k59rQgOlBJNJCWNB06KLWq /kbmK6Wa0jTscMTf2Kzo5USUFK9TckrHcpAzAYzPTtJdIVDZOJ01npmaxwRvoQ5V D84VVfKs73Pkpn1PwBVAVpOjn3VeE01vK+A+71kj0Jo9cPoyzqL/ObmJmjVI1MjP aEMRHDvQLl+Co59jjWYOWKyAEPhofo9mDVmCjDapHGppeAWH6E81AJYF6sG8K08Y VJutzsJbe9o9limkVzAGj2Z/i5lFCyX49NL0YBUO2iwDpNd2ijxDUUy+s4rLGyMK ehkgFjXp7qm91R5RAf/xkBtvTbEbQm/tbyYxGdnjN/Vpknpl1hk9O0QW6ItOqZUC FGZbvzn1fdT4xG7bWsaFmy1fwX8nwLPmCeKclQlnpGaBoai9b1Xu/au8QUku82Kb lNfhJeJLe8UiQvNHXmMZvDYGHIICAQApmuPEPjspsAmHYIJWWVPtq18A3Ac8jZ3a D1dq7sZqPD/7Lwl9Bci0froAioUhgaJgT4WCv4irhzpRjvz5ftN4D+iq41edoTQb XGLabaj9cXQqYD87uSB42+aHlCq3a+i+FOrh/NDKZb/tn8eaT/IKjSkl1LF6lbu/ 8yyMd3mncxFtRxtN9t1AXw== =NZ+q -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200901' into staging target-arm queue: * Implement fp16 support for AArch32 VFP and Neon * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes * hw/arm/sbsa-ref : Add embedded controller in secure memory # gpg: Signature made Tue 01 Sep 2020 16:17:23 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200901: (47 commits) hw/arm/sbsa-ref : Add embedded controller in secure memory hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref hw/arm/sbsa-ref: add "reg" property to DT cpu nodes target/arm: Enable FP16 in '-cpu max' target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations target/arm: Implement fp16 for Neon VRINTX target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode target/arm: Implement fp16 for Neon VCVT with rounding modes target/arm: Implement fp16 for Neon VCVT fixed-point target/arm: Convert Neon VCVT fixed-point to gvec target/arm: Implement fp16 for Neon float-integer VCVT target/arm: Implement fp16 for Neon pairwise fp ops target/arm: Implement fp16 for Neon VRSQRTS target/arm: Implement fp16 for Neon VRECPS target/arm: Implement fp16 for Neon fp compare-vs-0 target/arm: Implement fp16 for Neon VFMA, VMFS target/arm: Implement fp16 for Neon VMLA, VMLS operations target/arm: Implement fp16 for Neon VMAXNM, VMINNM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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