mirror of
https://github.com/qemu/qemu.git
synced 2024-12-21 11:13:48 +08:00
b7f1a0cb76
Commit ece09beec4 ("aspeed: introduce a configurable number of CPU
per machine") was a convient change during bringup but the Aspeed SoCs
have a fixed number of CPUs : one for the AST2400 and AST2500, and two
for the AST2600.
When the number of CPUs configured with -smp is less than the SoC's
fixed number, the "unconfigured" CPUs are left unrealized. This can
happen for machines ast2600-evb and tacoma-bmc, where the SoC's fixed
number is 2. To get virtual hardware that matches the physical
hardware, you have to pass -smp cpus=2 (or its sugared form -smp 2).
We normally reject -smp cpus=N when N exceeds the machine's limit.
Except we ignore cpus=2 (and only cpus=2) with a warning for machines
ast2500-evb, palmetto-bmc, romulus-bmc, sonorapass-bmc, swift-bmc, and
witherspoon-bmc.
Remove the "num-cpu" property from the SoC state and use the fixed
number of CPUs defined in the SoC class instead. Compute the default,
min, max number of CPUs of the machine directly from the SoC class
definition.
Machines ast2600-evb and tacoma-bmc now always get their second CPU as
they should. Visible in "info qom-tree"; here's the change for
ast2600-evb:
/machine (ast2600-evb-machine)
/peripheral (container)
/peripheral-anon (container)
/soc (ast2600-a1)
/a7mpcore (a15mpcore_priv)
/a15mp-priv-container[0] (qemu:memory-region)
/gic (arm_gic)
/gic_cpu[0] (qemu:memory-region)
/gic_cpu[1] (qemu:memory-region)
+ /gic_cpu[2] (qemu:memory-region)
/gic_dist[0] (qemu:memory-region)
/gic_vcpu[0] (qemu:memory-region)
/gic_viface[0] (qemu:memory-region)
/gic_viface[1] (qemu:memory-region)
+ /gic_viface[2] (qemu:memory-region)
/unnamed-gpio-in[0] (irq)
[...]
+ /unnamed-gpio-in[160] (irq)
[same for 161 to 190...]
+ /unnamed-gpio-in[191] (irq)
Also visible in "info qtree"; here's the change for ast2600-evb:
bus: main-system-bus
type System
dev: a15mpcore_priv, id ""
gpio-in "" 128
- gpio-out "sysbus-irq" 5
- num-cpu = 1 (0x1)
+ gpio-out "sysbus-irq" 10
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
mmio 0000000040460000/0000000000008000
dev: arm_gic, id ""
- gpio-in "" 160
- num-cpu = 1 (0x1)
+ gpio-in "" 192
+ num-cpu = 2 (0x2)
num-irq = 160 (0xa0)
revision = 2 (0x2)
has-security-extensions = true
has-virtualization-extensions = true
num-priority-bits = 8 (0x8)
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000001000
mmio ffffffffffffffff/0000000000002000
mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000100
+ mmio ffffffffffffffff/0000000000000200
mmio ffffffffffffffff/0000000000000200
The other machines now reject -smp cpus=2 just like -smp cpus=3 and up.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
[Commit message expanded]
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200609122339.937862-5-armbru@redhat.com>
139 lines
3.1 KiB
C
139 lines
3.1 KiB
C
/*
|
|
* ASPEED SoC family
|
|
*
|
|
* Andrew Jeffery <andrew@aj.id.au>
|
|
*
|
|
* Copyright 2016 IBM Corp.
|
|
*
|
|
* This code is licensed under the GPL version 2 or later. See
|
|
* the COPYING file in the top-level directory.
|
|
*/
|
|
|
|
#ifndef ASPEED_SOC_H
|
|
#define ASPEED_SOC_H
|
|
|
|
#include "hw/cpu/a15mpcore.h"
|
|
#include "hw/intc/aspeed_vic.h"
|
|
#include "hw/misc/aspeed_scu.h"
|
|
#include "hw/misc/aspeed_sdmc.h"
|
|
#include "hw/misc/aspeed_xdma.h"
|
|
#include "hw/timer/aspeed_timer.h"
|
|
#include "hw/rtc/aspeed_rtc.h"
|
|
#include "hw/i2c/aspeed_i2c.h"
|
|
#include "hw/ssi/aspeed_smc.h"
|
|
#include "hw/watchdog/wdt_aspeed.h"
|
|
#include "hw/net/ftgmac100.h"
|
|
#include "target/arm/cpu.h"
|
|
#include "hw/gpio/aspeed_gpio.h"
|
|
#include "hw/sd/aspeed_sdhci.h"
|
|
#include "hw/usb/hcd-ehci.h"
|
|
|
|
#define ASPEED_SPIS_NUM 2
|
|
#define ASPEED_EHCIS_NUM 2
|
|
#define ASPEED_WDTS_NUM 4
|
|
#define ASPEED_CPUS_NUM 2
|
|
#define ASPEED_MACS_NUM 4
|
|
|
|
typedef struct AspeedSoCState {
|
|
/*< private >*/
|
|
DeviceState parent;
|
|
|
|
/*< public >*/
|
|
ARMCPU cpu[ASPEED_CPUS_NUM];
|
|
A15MPPrivState a7mpcore;
|
|
MemoryRegion *dram_mr;
|
|
MemoryRegion sram;
|
|
AspeedVICState vic;
|
|
AspeedRtcState rtc;
|
|
AspeedTimerCtrlState timerctrl;
|
|
AspeedI2CState i2c;
|
|
AspeedSCUState scu;
|
|
AspeedXDMAState xdma;
|
|
AspeedSMCState fmc;
|
|
AspeedSMCState spi[ASPEED_SPIS_NUM];
|
|
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
|
|
AspeedSDMCState sdmc;
|
|
AspeedWDTState wdt[ASPEED_WDTS_NUM];
|
|
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
|
|
AspeedMiiState mii[ASPEED_MACS_NUM];
|
|
AspeedGPIOState gpio;
|
|
AspeedGPIOState gpio_1_8v;
|
|
AspeedSDHCIState sdhci;
|
|
AspeedSDHCIState emmc;
|
|
} AspeedSoCState;
|
|
|
|
#define TYPE_ASPEED_SOC "aspeed-soc"
|
|
#define ASPEED_SOC(obj) OBJECT_CHECK(AspeedSoCState, (obj), TYPE_ASPEED_SOC)
|
|
|
|
typedef struct AspeedSoCClass {
|
|
DeviceClass parent_class;
|
|
|
|
const char *name;
|
|
const char *cpu_type;
|
|
uint32_t silicon_rev;
|
|
uint64_t sram_size;
|
|
int spis_num;
|
|
int ehcis_num;
|
|
int wdts_num;
|
|
int macs_num;
|
|
const int *irqmap;
|
|
const hwaddr *memmap;
|
|
uint32_t num_cpus;
|
|
} AspeedSoCClass;
|
|
|
|
#define ASPEED_SOC_CLASS(klass) \
|
|
OBJECT_CLASS_CHECK(AspeedSoCClass, (klass), TYPE_ASPEED_SOC)
|
|
#define ASPEED_SOC_GET_CLASS(obj) \
|
|
OBJECT_GET_CLASS(AspeedSoCClass, (obj), TYPE_ASPEED_SOC)
|
|
|
|
enum {
|
|
ASPEED_IOMEM,
|
|
ASPEED_UART1,
|
|
ASPEED_UART2,
|
|
ASPEED_UART3,
|
|
ASPEED_UART4,
|
|
ASPEED_UART5,
|
|
ASPEED_VUART,
|
|
ASPEED_FMC,
|
|
ASPEED_SPI1,
|
|
ASPEED_SPI2,
|
|
ASPEED_EHCI1,
|
|
ASPEED_EHCI2,
|
|
ASPEED_VIC,
|
|
ASPEED_SDMC,
|
|
ASPEED_SCU,
|
|
ASPEED_ADC,
|
|
ASPEED_VIDEO,
|
|
ASPEED_SRAM,
|
|
ASPEED_SDHCI,
|
|
ASPEED_GPIO,
|
|
ASPEED_GPIO_1_8V,
|
|
ASPEED_RTC,
|
|
ASPEED_TIMER1,
|
|
ASPEED_TIMER2,
|
|
ASPEED_TIMER3,
|
|
ASPEED_TIMER4,
|
|
ASPEED_TIMER5,
|
|
ASPEED_TIMER6,
|
|
ASPEED_TIMER7,
|
|
ASPEED_TIMER8,
|
|
ASPEED_WDT,
|
|
ASPEED_PWM,
|
|
ASPEED_LPC,
|
|
ASPEED_IBT,
|
|
ASPEED_I2C,
|
|
ASPEED_ETH1,
|
|
ASPEED_ETH2,
|
|
ASPEED_ETH3,
|
|
ASPEED_ETH4,
|
|
ASPEED_MII1,
|
|
ASPEED_MII2,
|
|
ASPEED_MII3,
|
|
ASPEED_MII4,
|
|
ASPEED_SDRAM,
|
|
ASPEED_XDMA,
|
|
ASPEED_EMMC,
|
|
};
|
|
|
|
#endif /* ASPEED_SOC_H */
|