mirror of
https://github.com/qemu/qemu.git
synced 2024-11-25 03:43:37 +08:00
d2c753454e
The current XML files claim, on floating point-supporting Power chips, that $f0 is register 70. This would be fine, except that register 70 for non-XML-aware GDB is FPSCR. More importantly, 70 is less than NUM_CORE_REGS (71) for Power, so a request for register 70 goes to the "core" register reading routines, rather than the floating-point register read routine we registered with gdb_register_coprocessor. Therefore, when we are talking to an XML-aware GDB, we claim that register has zero width, which causes the rest of QEMU's GDB stub to send an error back to GDB, which causes GDB to be unable to read the floating-point registers. (The problem is also present for SPE registers and occurs in a slightly different way for Altivec registers.) The best way to fix this is to have the "core register" XML files for PPC32 and PPC64 claim that there is a 4-byte register 70, which causes $f0 to be register 71, and everything works just fine from that point forward. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6770 c046a42c-6fe2-441c-8c8c-71466251a162 |
||
|---|---|---|
| .. | ||
| arm-core.xml | ||
| arm-neon.xml | ||
| arm-vfp3.xml | ||
| arm-vfp.xml | ||
| cf-core.xml | ||
| cf-fp.xml | ||
| power64-core.xml | ||
| power-altivec.xml | ||
| power-core.xml | ||
| power-fpu.xml | ||
| power-spe.xml | ||