qemu/target
Daniel P. Berrangé 40b3cc354a i386: use better matching family/model/stepping for 'max' CPU
The 'max' CPU under TCG currently reports a family/model/stepping that
approximately corresponds to an AMD K7 vintage architecture.
The K7 series predates the introduction of 64-bit support by AMD
in the K8 series. This has been reported to lead to LLVM complaints
about generating 64-bit code for a 32-bit CPU target

  LLVM ERROR: 64-bit code requested on a subtarget that doesn't support it!

It appears LLVM looks at the family/model/stepping, despite qemu64
reporting it is 64-bit capable.

This patch changes 'max' to report a CPUID with the family, model
and stepping taken from a

 AMD Athlon(tm) 64 X2 Dual Core Processor 4000+

which is one of the first 64-bit AMD CPUs.

Closes https://gitlab.com/qemu-project/qemu/-/issues/191

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20210507133650.645526-3-berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2021-05-31 15:53:03 -04:00
..
alpha hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
arm hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
avr hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
cris hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
hexagon hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
hppa hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
i386 i386: use better matching family/model/stepping for 'max' CPU 2021-05-31 15:53:03 -04:00
m68k Adjust types for some memory access functions. 2021-05-28 16:25:21 +01:00
microblaze hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
mips hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
nios2 hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
openrisc hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
ppc hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
riscv hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
rx hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
s390x hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
sh4 hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
sparc hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
tricore hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
xtensa hw/core: Constify TCGCPUOps 2021-05-26 15:33:59 -07:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00