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2507c12ab0
As stated before, devices can be little, big or native endian. The target endianness is not of their concern, so we need to push things down a level. This patch adds a parameter to cpu_register_io_memory that allows a device to choose its endianness. For now, all devices simply choose native endian, because that's the same behavior as before. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
239 lines
6.6 KiB
C
239 lines
6.6 KiB
C
/*
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* Syborg interrupt controller.
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*
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* Copyright (c) 2008 CodeSourcery
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "sysbus.h"
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#include "syborg.h"
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//#define DEBUG_SYBORG_INT
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#ifdef DEBUG_SYBORG_INT
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#define DPRINTF(fmt, ...) \
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do { printf("syborg_int: " fmt , ## __VA_ARGS__); } while (0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "syborg_int: error: " fmt , ## __VA_ARGS__); \
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exit(1);} while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while(0)
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#define BADF(fmt, ...) \
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do { fprintf(stderr, "syborg_int: error: " fmt , ## __VA_ARGS__);} while (0)
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#endif
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enum {
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INT_ID = 0,
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INT_STATUS = 1, /* number of pending interrupts */
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INT_CURRENT = 2, /* next interrupt to be serviced */
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INT_DISABLE_ALL = 3,
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INT_DISABLE = 4,
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INT_ENABLE = 5,
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INT_TOTAL = 6
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};
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typedef struct {
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unsigned level:1;
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unsigned enabled:1;
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} syborg_int_flags;
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typedef struct {
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SysBusDevice busdev;
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int pending_count;
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uint32_t num_irqs;
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syborg_int_flags *flags;
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qemu_irq parent_irq;
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} SyborgIntState;
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static void syborg_int_update(SyborgIntState *s)
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{
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DPRINTF("pending %d\n", s->pending_count);
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qemu_set_irq(s->parent_irq, s->pending_count > 0);
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}
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static void syborg_int_set_irq(void *opaque, int irq, int level)
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{
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SyborgIntState *s = (SyborgIntState *)opaque;
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if (s->flags[irq].level == level)
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return;
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s->flags[irq].level = level;
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if (s->flags[irq].enabled) {
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if (level)
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s->pending_count++;
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else
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s->pending_count--;
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syborg_int_update(s);
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}
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}
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static uint32_t syborg_int_read(void *opaque, target_phys_addr_t offset)
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{
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SyborgIntState *s = (SyborgIntState *)opaque;
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int i;
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offset &= 0xfff;
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switch (offset >> 2) {
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case INT_ID:
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return SYBORG_ID_INT;
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case INT_STATUS:
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DPRINTF("read status=%d\n", s->pending_count);
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return s->pending_count;
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case INT_CURRENT:
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for (i = 0; i < s->num_irqs; i++) {
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if (s->flags[i].level & s->flags[i].enabled) {
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DPRINTF("read current=%d\n", i);
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return i;
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}
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}
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DPRINTF("read current=none\n");
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return 0xffffffffu;
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default:
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cpu_abort(cpu_single_env, "syborg_int_read: Bad offset %x\n",
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(int)offset);
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return 0;
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}
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}
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static void syborg_int_write(void *opaque, target_phys_addr_t offset, uint32_t value)
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{
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SyborgIntState *s = (SyborgIntState *)opaque;
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int i;
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offset &= 0xfff;
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DPRINTF("syborg_int_write offset=%d val=%d\n", (int)offset, (int)value);
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switch (offset >> 2) {
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case INT_DISABLE_ALL:
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s->pending_count = 0;
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for (i = 0; i < s->num_irqs; i++)
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s->flags[i].enabled = 0;
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break;
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case INT_DISABLE:
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if (value >= s->num_irqs)
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break;
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if (s->flags[value].enabled) {
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if (s->flags[value].enabled)
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s->pending_count--;
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s->flags[value].enabled = 0;
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}
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break;
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case INT_ENABLE:
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if (value >= s->num_irqs)
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break;
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if (!(s->flags[value].enabled)) {
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if(s->flags[value].level)
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s->pending_count++;
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s->flags[value].enabled = 1;
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}
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break;
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default:
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cpu_abort(cpu_single_env, "syborg_int_write: Bad offset %x\n",
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(int)offset);
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return;
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}
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syborg_int_update(s);
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}
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static CPUReadMemoryFunc * const syborg_int_readfn[] = {
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syborg_int_read,
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syborg_int_read,
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syborg_int_read
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};
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static CPUWriteMemoryFunc * const syborg_int_writefn[] = {
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syborg_int_write,
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syborg_int_write,
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syborg_int_write
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};
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static void syborg_int_save(QEMUFile *f, void *opaque)
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{
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SyborgIntState *s = (SyborgIntState *)opaque;
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int i;
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qemu_put_be32(f, s->num_irqs);
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qemu_put_be32(f, s->pending_count);
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for (i = 0; i < s->num_irqs; i++) {
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qemu_put_be32(f, s->flags[i].enabled
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| ((unsigned)s->flags[i].level << 1));
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}
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}
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static int syborg_int_load(QEMUFile *f, void *opaque, int version_id)
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{
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SyborgIntState *s = (SyborgIntState *)opaque;
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uint32_t val;
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int i;
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if (version_id != 1)
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return -EINVAL;
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val = qemu_get_be32(f);
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if (val != s->num_irqs)
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return -EINVAL;
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s->pending_count = qemu_get_be32(f);
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for (i = 0; i < s->num_irqs; i++) {
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val = qemu_get_be32(f);
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s->flags[i].enabled = val & 1;
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s->flags[i].level = (val >> 1) & 1;
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}
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return 0;
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}
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static int syborg_int_init(SysBusDevice *dev)
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{
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SyborgIntState *s = FROM_SYSBUS(SyborgIntState, dev);
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int iomemtype;
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sysbus_init_irq(dev, &s->parent_irq);
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qdev_init_gpio_in(&dev->qdev, syborg_int_set_irq, s->num_irqs);
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iomemtype = cpu_register_io_memory(syborg_int_readfn,
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syborg_int_writefn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio(dev, 0x1000, iomemtype);
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s->flags = qemu_mallocz(s->num_irqs * sizeof(syborg_int_flags));
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register_savevm(&dev->qdev, "syborg_int", -1, 1, syborg_int_save,
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syborg_int_load, s);
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return 0;
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}
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static SysBusDeviceInfo syborg_int_info = {
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.init = syborg_int_init,
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.qdev.name = "syborg,interrupt",
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.qdev.size = sizeof(SyborgIntState),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-interrupts", SyborgIntState, num_irqs, 64),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void syborg_interrupt_register_devices(void)
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{
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sysbus_register_withprop(&syborg_int_info);
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}
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device_init(syborg_interrupt_register_devices)
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