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40061ac0bc
The watermark bits are set in the interrupt pending register according to the configuration of txcnt and rxcnt in the txctrl and rxctrl registers. Since the UART TX does not implement a FIFO, the txwm bit is set as long as the TX watermark level is greater than zero. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
191 lines
4.6 KiB
C
191 lines
4.6 KiB
C
/*
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* QEMU model of the UART on the SiFive E300 and U500 series SOCs.
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*
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* Copyright (c) 2016 Stefan O'Rear
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "chardev/char.h"
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#include "chardev/char-fe.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/sifive_uart.h"
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/*
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* Not yet implemented:
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*
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* Transmit FIFO using "qemu/fifo8.h"
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*/
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/* Returns the state of the IP (interrupt pending) register */
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static uint64_t uart_ip(SiFiveUARTState *s)
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{
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uint64_t ret = 0;
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uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl);
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uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl);
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if (txcnt != 0) {
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ret |= SIFIVE_UART_IP_TXWM;
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}
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if (s->rx_fifo_len > rxcnt) {
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ret |= SIFIVE_UART_IP_RXWM;
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}
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return ret;
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}
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static void update_irq(SiFiveUARTState *s)
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{
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int cond = 0;
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if ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len) {
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cond = 1;
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}
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if (cond) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static uint64_t
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uart_read(void *opaque, hwaddr addr, unsigned int size)
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{
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SiFiveUARTState *s = opaque;
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unsigned char r;
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switch (addr) {
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case SIFIVE_UART_RXFIFO:
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if (s->rx_fifo_len) {
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r = s->rx_fifo[0];
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memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
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s->rx_fifo_len--;
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qemu_chr_fe_accept_input(&s->chr);
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update_irq(s);
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return r;
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}
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return 0x80000000;
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case SIFIVE_UART_TXFIFO:
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return 0; /* Should check tx fifo */
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case SIFIVE_UART_IE:
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return s->ie;
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case SIFIVE_UART_IP:
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return uart_ip(s);
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case SIFIVE_UART_TXCTRL:
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return s->txctrl;
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case SIFIVE_UART_RXCTRL:
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return s->rxctrl;
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case SIFIVE_UART_DIV:
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return s->div;
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}
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hw_error("%s: bad read: addr=0x%x\n",
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__func__, (int)addr);
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return 0;
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}
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static void
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uart_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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SiFiveUARTState *s = opaque;
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uint32_t value = val64;
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unsigned char ch = value;
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switch (addr) {
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case SIFIVE_UART_TXFIFO:
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qemu_chr_fe_write(&s->chr, &ch, 1);
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return;
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case SIFIVE_UART_IE:
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s->ie = val64;
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update_irq(s);
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return;
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case SIFIVE_UART_TXCTRL:
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s->txctrl = val64;
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return;
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case SIFIVE_UART_RXCTRL:
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s->rxctrl = val64;
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return;
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case SIFIVE_UART_DIV:
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s->div = val64;
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return;
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}
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hw_error("%s: bad write: addr=0x%x v=0x%x\n",
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__func__, (int)addr, (int)value);
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}
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static const MemoryRegionOps uart_ops = {
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.read = uart_read,
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.write = uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4
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}
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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SiFiveUARTState *s = opaque;
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/* Got a byte. */
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if (s->rx_fifo_len >= sizeof(s->rx_fifo)) {
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printf("WARNING: UART dropped char.\n");
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return;
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}
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s->rx_fifo[s->rx_fifo_len++] = *buf;
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update_irq(s);
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}
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static int uart_can_rx(void *opaque)
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{
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SiFiveUARTState *s = opaque;
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return s->rx_fifo_len < sizeof(s->rx_fifo);
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}
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static void uart_event(void *opaque, int event)
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{
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}
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static int uart_be_change(void *opaque)
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{
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SiFiveUARTState *s = opaque;
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qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
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uart_be_change, s, NULL, true);
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return 0;
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}
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/*
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* Create UART device.
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*/
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SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
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Chardev *chr, qemu_irq irq)
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{
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SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
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s->irq = irq;
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qemu_chr_fe_init(&s->chr, chr, &error_abort);
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qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
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uart_be_change, s, NULL, true);
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memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
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TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
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memory_region_add_subregion(address_space, base, &s->mmio);
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return s;
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}
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