mirror of
https://github.com/qemu/qemu.git
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194eef09d0
Previously the second UARTs on the sifive_e and sifive_u machines where disabled due to check-qtest-riscv32 and check-qtest-riscv64 failures. Recent changes in the QEMU core serial code have resolved these failures so the second UARTs can be instantiated. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
429 lines
17 KiB
C
429 lines
17 KiB
C
/*
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* QEMU RISC-V Board Compatible with SiFive Freedom U SDK
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Provides a board compatible with the SiFive Freedom U SDK:
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*
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* 0) UART
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* 1) CLINT (Core Level Interruptor)
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* 2) PLIC (Platform Level Interrupt Controller)
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*
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* This board currently uses a hardcoded devicetree that indicates one hart.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_plic.h"
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#include "hw/riscv/sifive_clint.h"
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#include "hw/riscv/sifive_uart.h"
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#include "hw/riscv/sifive_prci.h"
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#include "hw/riscv/sifive_u.h"
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#include "chardev/char.h"
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#include "sysemu/arch_init.h"
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#include "sysemu/device_tree.h"
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#include "exec/address-spaces.h"
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#include "elf.h"
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#include <libfdt.h>
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static const struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} sifive_u_memmap[] = {
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[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
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[SIFIVE_U_MROM] = { 0x1000, 0x11000 },
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[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_U_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_U_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
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[SIFIVE_U_GEM] = { 0x100900FC, 0x2000 },
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};
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#define GEM_REVISION 0x10070109
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static uint64_t load_kernel(const char *kernel_filename)
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{
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uint64_t kernel_entry, kernel_high;
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if (load_elf(kernel_filename, NULL, NULL,
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&kernel_entry, NULL, &kernel_high,
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0, EM_RISCV, 1, 0) < 0) {
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error_report("could not load kernel '%s'", kernel_filename);
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exit(1);
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}
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return kernel_entry;
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}
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static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
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uint64_t mem_size, const char *cmdline)
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{
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void *fdt;
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int cpu;
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uint32_t *cells;
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char *nodename;
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char ethclk_names[] = "pclk\0hclk\0tx_clk";
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uint32_t plic_phandle, ethclk_phandle;
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fdt = s->fdt = create_device_tree(&s->fdt_size);
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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nodename = g_strdup_printf("/memory@%lx",
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(long)memmap[SIFIVE_U_DRAM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
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mem_size >> 32, mem_size);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
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g_free(nodename);
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qemu_fdt_add_subnode(fdt, "/cpus");
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qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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SIFIVE_CLINT_TIMEBASE_FREQ);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
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for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) {
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nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_CLOCK_FREQ);
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qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
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qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
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qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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qemu_fdt_add_subnode(fdt, intc);
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qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
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qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
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qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
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qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
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g_free(isa);
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g_free(intc);
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g_free(nodename);
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}
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cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
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for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/clint@%lx",
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(long)memmap[SIFIVE_U_CLINT].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_CLINT].base,
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0x0, memmap[SIFIVE_U_CLINT].size);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
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g_free(cells);
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g_free(nodename);
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cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4);
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for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) {
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nodename =
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g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
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cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
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g_free(nodename);
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}
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nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
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(long)memmap[SIFIVE_U_PLIC].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
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qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4);
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_PLIC].base,
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0x0, memmap[SIFIVE_U_PLIC].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
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qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
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qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
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qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
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plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(cells);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethclk");
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_GEM_CLOCK_FREQ);
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qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3);
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qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3);
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ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethernet@%lx",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_GEM].base,
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0x0, memmap[SIFIVE_U_GEM].size);
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qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
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qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
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qemu_fdt_setprop_cells(fdt, nodename, "clocks",
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ethclk_phandle, ethclk_phandle, ethclk_phandle);
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qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names,
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sizeof(ethclk_names));
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qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1);
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qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
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(long)memmap[SIFIVE_U_GEM].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0);
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g_free(nodename);
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nodename = g_strdup_printf("/soc/uart@%lx",
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(long)memmap[SIFIVE_U_UART0].base);
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qemu_fdt_add_subnode(fdt, nodename);
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qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
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qemu_fdt_setprop_cells(fdt, nodename, "reg",
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0x0, memmap[SIFIVE_U_UART0].base,
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0x0, memmap[SIFIVE_U_UART0].size);
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qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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SIFIVE_U_CLOCK_FREQ / 2);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
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qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
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if (cmdline) {
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qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
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}
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g_free(nodename);
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}
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static void riscv_sifive_u_init(MachineState *machine)
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{
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const struct MemmapEntry *memmap = sifive_u_memmap;
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SiFiveUState *s = g_new0(SiFiveUState, 1);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *main_mem = g_new(MemoryRegion, 1);
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int i;
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/* Initialize SoC */
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object_initialize_child(OBJECT(machine), "soc", &s->soc,
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sizeof(s->soc), TYPE_RISCV_U_SOC,
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&error_abort, NULL);
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object_property_set_bool(OBJECT(&s->soc), true, "realized",
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&error_abort);
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/* register RAM */
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memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
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machine->ram_size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
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main_mem);
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/* create device tree */
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create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
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if (machine->kernel_filename) {
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load_kernel(machine->kernel_filename);
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}
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/* reset vector */
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uint32_t reset_vec[8] = {
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0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
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0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
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0xf1402573, /* csrr a0, mhartid */
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#if defined(TARGET_RISCV32)
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0x0182a283, /* lw t0, 24(t0) */
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#elif defined(TARGET_RISCV64)
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0x0182b283, /* ld t0, 24(t0) */
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#endif
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0x00028067, /* jr t0 */
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0x00000000,
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memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
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0x00000000,
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/* dtb: */
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};
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/* copy in the reset vector in little_endian byte order */
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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}
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_U_MROM].base, &address_space_memory);
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/* copy in the device tree */
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if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
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memmap[SIFIVE_U_MROM].size - sizeof(reset_vec)) {
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error_report("not enough space to store device-tree");
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exit(1);
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}
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qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
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rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
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memmap[SIFIVE_U_MROM].base + sizeof(reset_vec),
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&address_space_memory);
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}
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static void riscv_sifive_u_soc_init(Object *obj)
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{
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SiFiveUSoCState *s = RISCV_U_SOC(obj);
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object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus),
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TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
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object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type",
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&error_abort);
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object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts",
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&error_abort);
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sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem),
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TYPE_CADENCE_GEM);
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}
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static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp)
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{
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SiFiveUSoCState *s = RISCV_U_SOC(dev);
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const struct MemmapEntry *memmap = sifive_u_memmap;
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
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qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
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int i;
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Error *err = NULL;
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NICInfo *nd = &nd_table[0];
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object_property_set_bool(OBJECT(&s->cpus), true, "realized",
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&error_abort);
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/* boot rom */
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memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom",
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memmap[SIFIVE_U_MROM].size, &error_fatal);
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memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
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mask_rom);
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/* MMIO */
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s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
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(char *)SIFIVE_U_PLIC_HART_CONFIG,
|
|
SIFIVE_U_PLIC_NUM_SOURCES,
|
|
SIFIVE_U_PLIC_NUM_PRIORITIES,
|
|
SIFIVE_U_PLIC_PRIORITY_BASE,
|
|
SIFIVE_U_PLIC_PENDING_BASE,
|
|
SIFIVE_U_PLIC_ENABLE_BASE,
|
|
SIFIVE_U_PLIC_ENABLE_STRIDE,
|
|
SIFIVE_U_PLIC_CONTEXT_BASE,
|
|
SIFIVE_U_PLIC_CONTEXT_STRIDE,
|
|
memmap[SIFIVE_U_PLIC].size);
|
|
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
|
|
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
|
|
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
|
|
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
|
|
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
|
|
memmap[SIFIVE_U_CLINT].size, smp_cpus,
|
|
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
|
|
|
|
for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
|
|
plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
|
|
}
|
|
|
|
if (nd->used) {
|
|
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
|
|
qdev_set_nic_properties(DEVICE(&s->gem), nd);
|
|
}
|
|
object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision",
|
|
&error_abort);
|
|
object_property_set_bool(OBJECT(&s->gem), true, "realized", &err);
|
|
if (err) {
|
|
error_propagate(errp, err);
|
|
return;
|
|
}
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
|
|
plic_gpios[SIFIVE_U_GEM_IRQ]);
|
|
}
|
|
|
|
static void riscv_sifive_u_machine_init(MachineClass *mc)
|
|
{
|
|
mc->desc = "RISC-V Board compatible with SiFive U SDK";
|
|
mc->init = riscv_sifive_u_init;
|
|
mc->max_cpus = 1;
|
|
}
|
|
|
|
DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)
|
|
|
|
static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = riscv_sifive_u_soc_realize;
|
|
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
|
|
dc->user_creatable = false;
|
|
}
|
|
|
|
static const TypeInfo riscv_sifive_u_soc_type_info = {
|
|
.name = TYPE_RISCV_U_SOC,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(SiFiveUSoCState),
|
|
.instance_init = riscv_sifive_u_soc_init,
|
|
.class_init = riscv_sifive_u_soc_class_init,
|
|
};
|
|
|
|
static void riscv_sifive_u_soc_register_types(void)
|
|
{
|
|
type_register_static(&riscv_sifive_u_soc_type_info);
|
|
}
|
|
|
|
type_init(riscv_sifive_u_soc_register_types)
|